参数资料
型号: DS1021S-25
厂商: DALLAS SEMICONDUCTOR
元件分类: Delay Line
英文描述: SILICON DELAY LINE, TRUE OUTPUT, PDSO16
封装: 0.300 INCH, SOIC-16
文件页数: 6/9页
文件大小: 193K
代理商: DS1021S-25
DS1021
6 of 9
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
-1.0V to +7.0V
Operating Temperature
0
°C to 70°C
Storage Temperature
-55
°C to +125°C
Soldering Temperature
260
°C for 10 seconds
Short Circuit Output Current
50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 5.0V ± 5%)
PARAMETER
SYM
TEST
CONDITION
MIN
TYP
MAX
UNITS
NOTES
Supply Voltage
VCC
4.75
5.00
5.25
V
1
High Level Input
Voltage
VIH
2.2
VCC + 0.5
V
1
Low Level Input
Voltage
VIL
-0.5
0.8
V
1
Input Leakage
Current
I1
0.0V
≤ VI ≤ VCC
-1.0
1.0
A
Active Current
ICC
VCC=MAX;
Period=1 s
30.0
mA
3
High Level Output
Current
IOH
VCC=MIN.
VOH=2.7V
-1.0
mA
Low Level Output
Current
IOL
VCC=MIN.
VOL=0.5V
8mA
4
AC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 5V ± 5%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Clock Frequency
fC
10
MHz
Enable Width
tEW
50
ns
Fig. 7, 8
Clock Width
tCW
50
ns
Fig. 8
Data Setup to Clock
tDSC
30
ns
Fig. 8
Data Hold from Clock
tDHC
10
ns
Fig. 8
Data Setup to Enable
tDSE
30
ns
Fig. 7
Data Hold from Enable
tDHE
20
ns
Fig. 7
Enable to Serial
Output Valid
tEQV
50
ns
Fig. 8
Enable to Serial
Output High Z
tEQZ
0
50
ns
Fig. 8
Clock to Serial
Output Valid
tCQV
50
ns
Fig. 8
Clock to Serial
Output Invalid
tCQX
10
ns
Fig. 8
Enable Setup to Clock
tES
50
ns
Fig. 8
Enable Hold from Clock
tEH
50
ns
Fig. 8
Parallel Input Valid
to Delay Valid
tPDV
50
s
Fig. 6
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