参数资料
型号: DS1021S-50
厂商: DALLAS SEMICONDUCTOR
元件分类: Delay Line
英文描述: SILICON DELAY LINE, TRUE OUTPUT, PDSO16
封装: 0.300 INCH, SOIC-16
文件页数: 5/9页
文件大小: 193K
代理商: DS1021S-50
DS1021
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DALLAS SEMICONDUCTOR TEST CIRCUIT Figure 4
TEST SETUP DESCRIPTION
Figure 4 illustrates the hardware configuration used for measuring the timing parameters of the DS1021.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected to the output. The DS1021 serial and
parallel ports are controlled by interfaces to a central computer. All measurements are fully automated
with each instrument controlled by the computer over an IEEE 488 bus.
TEST CONDITIONS
INPUT:
Ambient Temperature:
25°C ± 3°C
Supply Voltage (VCC):
5.0V ± 0.1V
Input Pulse:
High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
Source Impedance:
50 ohms max.
Rise and Fall Time:
3.0 ns max.
(measured between 0.6V and 2.4V)
Pulse Width:
500 ns (DS1021–25)
2 s (DS1021–50)
Period:
1 s (DS1021–25)
4 s (DS1021–50)
NOTE: Above conditions are for test only and do not restrict the operation of the device under other data
sheet conditions.
OUTPUT:
Output is loaded with a 74F04. Delay is measured between the 1.5V level of the rising edge of the input
signal and the 1.5V level of the corresponding edge of the output.
DS1021
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相关代理商/技术参数
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