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参数资料
| 型号： | DS1023S-200+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 9/16页 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 256TAP 16-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 45 |
| 标片/步级数： | 256 |
| 功能： | 单发射，可编程 |
| 延迟到第一抽头： | 16.5ns |
| 接头增量： | 2ns |
| 可用的总延迟： | 510ns |
| 独立延迟数： | 1 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 管件 |
DS1023
2 of 16
On-chip gating is provided to allow the device to provide a pulse width modulated output, triggered by
the input with duration set by the programmed value.
Alternatively the output signal may be inverted on chip, allowing the device to perform as a free-running
oscillator if the output is (externally) connected to the input.
PROGRAMMING
The device programming is identical to the DS1020/DS1021. Note, however, that the serial clock and
data pins are shared with three of the parallel input pins.
The P /S pin controls the same function as “Mode Select” on the DS1020/DS1021 (but with reversed
polarity). A low logic level on this pin enables the parallel programming mode. LE must be at a high
logic level to alter the programmed value; when LE is taken low the data is latched internally and the
parallel data inputs may be altered without affecting the programmed value.
This is useful for
multiplexed bus applications. For hard-wired applications LE should be tied to a high logic level.
When P /S is high serial programming is enabled. LE must be held high to enable loading or reading of
the internal register, during which time the delay is determined by the previously programmed value.
Data is clocked in MSB to LSB order on the rising edge of the CLK input. Data transfer ends and the
new value is activated when LE is taken low.
PARALLEL MODE ( P /S = 0)
In the PARALLEL programming mode, the output of the DS1023 will reproduce the logic state of the
input after a delay determined by the state of the eight program input pins P0 - P7. The parallel inputs
can be programmed using DC levels or computer-generated data. For infrequent modification of the
delay value, jumpers may be used to connect the input pins to VCC or ground. For applications requiring
frequent timing adjustment, DIP switches may be used. The latch enable pin (LE) must be at a logic 1 in
hardwired implementations.
Maximum flexibility is obtained when the eight parallel programming bits are set using computer-
generated data. When the data setup (tDSE) and data hold (tDHE) requirements are observed, the enable pin
can be used to latch data supplied on an 8-bit bus. Latch enable must be held at a logic 1 if it is not used
to latch the data. After each change in delay value, a settling time (tEDV or tPDV) is required before input
logic levels are accurately delayed.
SERIAL MODE ( P /S = 1)
In the SERIAL programming mode, the output of the DS1023 will reproduce the logic state of the input
after a delay time determined by an 8-bit value clocked into serial port D. While observing data setup
(tDSC) and data hold (tDHC) requirements, timing data is loaded in MSB-to-LSB order by the rising edge of
the serial clock (CLK). The latch enable pin (LE) must be at a logic 1 to load or read the internal 8-bit
input register, during which time the delay is determined by the last value activated. Data transfer ends
and the new delay value is activated when latch enable (LE) returns to a logic 0. After each change, a
settling time (tEDV) is required before the delay is accurate.
As timing values are shifted into the serial data input (D), the previous contents of the 8-bit input register
are shifted out of the serial output pin (Q) in MSB-to-LSB order. By connecting the serial output of one
DS1023 to the serial input of a second DS1023, multiple devices can be daisy-chained (cascaded) for
programming purposes (Figure 1). The total number of serial bits must be eight times the number of units
daisy-chained and each group of 8 bits must be sent in MSB-to-LSB order.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1023S-200/T&R | 制造商:Maxim Integrated Products 功能描述:PRG 8BIT DLAY 2.00NS STPS SO T&R - Tape and Reel 制造商:Maxim Integrated Products 功能描述:Delay Lines / Timing Elements Programmable 8-Bit 2ns Timing Element |
| DS1023S-200/T&R | 功能描述:延迟线/计时元素 Programmable 8-Bit 2ns Timing Element RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| DS1023S-200+ | 功能描述:延迟线/计时元素 Programmable 8-Bit 2ns Timing Element RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| DS1023S-200+T&R | 制造商:Maxim Integrated Products 功能描述:ACTV PROGRAMMABLE DLY LINE 1-IN 2NS ABS 510NS MAX 16SOIC W - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC DEL LINE 256TAP 510NS 16SOIC 制造商:Maxim Integrated Products 功能描述:Delay Lines / Timing Elements Programmable 8-Bit 2ns Timing Element |
| DS1023S-200+T&R | 功能描述:延迟线/计时元素 Programmable 8-Bit 2ns Timing Element RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
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