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参数资料
| 型号： | DS1050Z-1/T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 17/17页 |
| 文件大小： | 0K |
| 描述： | IC PWM 5-BIT 1KHZ 2-WIRE 8-SOIC |
| 标准包装： | 2,500 |
| 类型： | 脉宽调制器（PWM） |
| PLL： | 无 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 1kHz |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | * |
| 包装： | 带卷 (TR) |
DS1050
9 of 17
NOTES:
1.
All voltages are referenced to ground.
2.
ICC specified with outputs open.
3.
I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VCC is switched off.
4.
Address Inputs, A0, A1, and A2, should be tied to either VCC or GND depending on the desired
address selections.
5.
ISTBY specified for VCC between 3.0V and 5.0V, control port logic pins are driven to the appropriate
logic levels.
6.
A fast mode device can be used in a standard mode system, but the requirement
tSU:DAT > 250ns must then be met. This will automatically be the case if the device does not stretch
the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000 + 250=1250ns before the SCL
line is released.
7.
After this period, the first clock pulse is generated.
8.
The maximum tSU:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL signal.
9.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
VIH MIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
10. CB – total capacitance of one bus line in picofarads, timing referenced to (0.9)(VCC) and (0.1)(VCC).
11. A PWM output duty cycle change will occur with 2 periods of the output frequency when a change is
initiated.
12. The absolute frequency output of the PWM can be expected to fall within a
±20% range from the
nominal specified value of the device.
13. The DS1050 is a 5-bit PWM. The output duty cycles of the device range from 0% to 100% in step
sizes of 3.125%. The “Set PWM Duty Cycle 100%” allows the PWM output to be set to full-on.
14. Absolute Linearity is used to compare measured duty cycle against expected duty cycle as
determined by the DAC setting. The DS1050 is specified to provide an absolute linearity of
±0.5
LSB.
15. Relative Linearity is used to determine the change in duty cycle between adjacent or successive duty
cycle settings. The DS1050 is specified to provide a relative linearity specification of
±0.25 LSB.
相关PDF资料 |
PDF描述 |
|---|---|
| DS1050Z-10/T&R | IC PWM 5-BIT 10KHZ 2-WIRE 8-SOIC |
| DS1050P-5/T&R | IC PWM 5-BIT 5KHZ 2-WIRE 8-USOP |
| VI-2NN-IW-B1 | CONVERTER MOD DC/DC 18.5V 100W |
| DS1050P-1/T&R | IC PWM 5-BIT 1KHZ 2-WIRE 8-USOP |
| VI-2NM-IW-B1 | CONVERTER MOD DC/DC 10V 100W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1050Z-25 | 功能描述:IC PWM 5BIT 25KHZ 2-WIRE 8SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| DS1050Z-25/T&R | 制造商:Maxim Integrated Products 功能描述:PROG PWM 8P SOIC 25KHZ 2-W T&R - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC PWM 5-BIT 25KHZ 2-WIRE 8-SOIC |
| DS1050Z-25/T&R | 功能描述:IC PWM 5-BIT 25KHZ 2-WIRE 8-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| DS1050Z-5/T&R | 制造商:Maxim Integrated Products 功能描述:IC CLK PWM 5KHZ 1CIRC 8SOIC |
| DS1050Z-5/T&R | 功能描述:IC PWM 5-BIT 5KHZ 2-WIRE 8-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
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