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参数资料
| 型号： | DS1077Z-125 |
| 厂商： | DALLAS SEMICONDUCTOR |
| 元件分类： | Clock Generator |
| 英文描述： | 125 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | 0.150 INCH, SOIC-8 |
| 文件页数： | 16/17页 |
| 文件大小： | 103K |
| 代理商： | DS1077Z-125 |
DS1077
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Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is
HIGH, defines a START condition.
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is
HIGH, defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line is
stable for the duration of the HIGH period of the clock signal. The data on the line must be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited, and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a
ninth bit.
Within the bus specifications a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are
defined. The DS1077 works in both modes.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is associated with
this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. When the DS1077 EEPROM is being written to,
it will not be able to perform additional responses. In this case, the slave DS1077 will send a not
acknowledge to any data transfer request made by the master. It will resume normal operation when the
EEPROM operation is complete.
A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that
has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the
master to generate the STOP condition.
相关PDF资料 |
PDF描述 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1077Z-125+ | 功能描述:可编程振荡器 EconOscillator/Dvdr 125MHz 118mil 2-Wire RoHS:否 制造商:IDT 封装 / 箱体:5 mm x 7 mm x 1.5 mm 频率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 频率稳定性:+/- 50 PPM 电源电压:3.63 V 负载电容:10 pF 端接类型:SMD/SMT 输出格式:LVPECL 最小工作温度:- 40 C 最大工作温度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封装: |
| DS1077Z-125+T&R | 制造商:Maxim Integrated Products 功能描述:ECO OSC 125MHZ 2-WIRE 8P-SO TRL LF - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC ECONOSCILLATOR 125MHZ 8SOIC |
| DS1077Z-125+T&R | 功能描述:可编程振荡器 EconOscillator/Dvdr 125MHz 118mil 2-Wire RoHS:否 制造商:IDT 封装 / 箱体:5 mm x 7 mm x 1.5 mm 频率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 频率稳定性:+/- 50 PPM 电源电压:3.63 V 负载电容:10 pF 端接类型:SMD/SMT 输出格式:LVPECL 最小工作温度:- 40 C 最大工作温度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封装: |
| DS1077Z-133 | 功能描述:可编程振荡器 EconOscillator/Dvdr 133MHz 118mil 2-Wire RoHS:否 制造商:IDT 封装 / 箱体:5 mm x 7 mm x 1.5 mm 频率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 频率稳定性:+/- 50 PPM 电源电压:3.63 V 负载电容:10 pF 端接类型:SMD/SMT 输出格式:LVPECL 最小工作温度:- 40 C 最大工作温度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封装: |
| DS1077Z-133+ | 功能描述:可编程振荡器 EconOscillator/Dvdr 133MHz 118mil 2-Wire RoHS:否 制造商:IDT 封装 / 箱体:5 mm x 7 mm x 1.5 mm 频率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 频率稳定性:+/- 50 PPM 电源电压:3.63 V 负载电容:10 pF 端接类型:SMD/SMT 输出格式:LVPECL 最小工作温度:- 40 C 最大工作温度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封装: |
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