参数资料
型号: DS1085LZ-12B2+
厂商: Maxim Integrated Products
文件页数: 11/21页
文件大小: 0K
描述: IC ECONOSCILLATOR SYNTH 8-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 100
系列: EconOscillator™
类型: 频率合成器
PLL:
输入: 时钟
输出: 时钟
电路数: 1
比率 - 输入:输出: 1:2
差分 - 输入:输出: 无/无
频率 - 最大: 66MHz
除法器/乘法器: 是/无
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
DS1085L
19 of 21
7) DAC and OFFSET register settings must be configured to maintain the clock frequency within this
range. Correct operation of the device is not guaranteed if these limits are exceeded.
8) Frequency settles faster for small charges in value. During a change, the frequency changes smoothly
from the original value to the new value.
9) This indicates the time taken between power-up and the outputs becoming active. An on-chip delay is
intentionally introduced to allow the oscillator to stabilize. tstab is equivalent to approximately 8000
clock cycles and hence depends on the programmed clock frequency.
10) Output voltage swings can be impaired at high frequencies combined with high-output loading.
11) After this period, the first clock pulse is generated.
12) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
VIH MIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
13) The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW ) of the
SCL signal.
14) A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL
signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line at least tR MAX + tSU:DAT = 1000ns + 250ns = 1250ns before the SCL line is
released.
15) CB—total capacitance of one bus line in picofarads; timing referenced to 0.9VCC and 0.1VCC.
16) EEPROM write begins after a STOP condition occurs.
17) Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 1 moisture reflow preconditioning (24hr
+125
°C bake, 168hr 85°C/85%RH moisture soak, and 3 solder reflow passes +240 +0/-5°C peak) followed by 1000hr max
VCC biased 125
°C HTOL, 1000 temperature cycles at -55°C to +125°C, 96hr 130°C/85%RH/5.5V HAST and 168hr 121°C/2
ATM Steam/Unbiased Autoclave.
Figure 5. MASTER FREQUENCY TEMPERATURE VARIATION
MASTER FREQUENCY TEMPERATURE
VARIATION
-2.00
-1.50
-1.00
-0.50
0.00
0.50
1.00
1.50
2.00
33
41.25
49.5
57.75
66
MASTER OSCILLATOR FREQUENCY (MHz)
FREQUENCY
%
CHANGE
FROM
2
C
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DS1085LZ-25 功能描述:可编程振荡器 3.3V EconOscillator f Synthesizer RoHS:否 制造商:IDT 封装 / 箱体:5 mm x 7 mm x 1.5 mm 频率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 频率稳定性:+/- 50 PPM 电源电压:3.63 V 负载电容:10 pF 端接类型:SMD/SMT 输出格式:LVPECL 最小工作温度:- 40 C 最大工作温度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封装:
DS1085LZ-25+ 功能描述:可编程振荡器 3.3V EconOscillator f Synthesizer RoHS:否 制造商:IDT 封装 / 箱体:5 mm x 7 mm x 1.5 mm 频率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 频率稳定性:+/- 50 PPM 电源电压:3.63 V 负载电容:10 pF 端接类型:SMD/SMT 输出格式:LVPECL 最小工作温度:- 40 C 最大工作温度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封装:
DS1085LZ-25B2 功能描述:可编程振荡器 RoHS:否 制造商:IDT 封装 / 箱体:5 mm x 7 mm x 1.5 mm 频率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 频率稳定性:+/- 50 PPM 电源电压:3.63 V 负载电容:10 pF 端接类型:SMD/SMT 输出格式:LVPECL 最小工作温度:- 40 C 最大工作温度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封装:
DS1085LZ-25B2+ 功能描述:可编程振荡器 3.3V EconOscillator f Synthesizer RoHS:否 制造商:IDT 封装 / 箱体:5 mm x 7 mm x 1.5 mm 频率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 频率稳定性:+/- 50 PPM 电源电压:3.63 V 负载电容:10 pF 端接类型:SMD/SMT 输出格式:LVPECL 最小工作温度:- 40 C 最大工作温度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封装: