参数资料
型号: DS1086Z
厂商: Maxim Integrated Products
文件页数: 15/15页
文件大小: 0K
描述: IC ECONOSCILLATOR SS 8-SOIC
其它有关文件: Automotive Product Guide
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 100
系列: EconOscillator™
类型: 扩展频谱时钟发生器
PLL:
输入: 时钟
输出: 时钟
电路数: 1
比率 - 输入:输出: 2:1
差分 - 输入:输出: 无/无
频率 - 最大: 133MHz
除法器/乘法器: 是/无
电源电压: 4.75 V ~ 5.25 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
DS1086
Spread-Spectrum EconOscillator
_______________________________________________________________________________________
9
The output frequency is determined by the following
equation:
where:
min frequency of selected OFFSET range is the
lowest frequency (shown in Table 2 for the correspond-
ing offset).
DAC value is the value of the DAC register (0 to 1023).
Prescaler is the value of 2x where x = 0 to 8.
See the
Example Frequency Calculations section for a
more in-depth look at using the registers.
________________Register Definitions
The DS1086 registers are used to determine the output
frequency and dither amount. A summary of the regis-
ters is shown in Table 1. Using the default register set-
tings below, the default output frequency is 97.1MHz.
See the
Example Frequency Calculations section for an
example on how to determine the register settings for a
desired output frequency.
PRESCALER Register
The PRESCALER register controls the prescaler (bits P3
to P0) and dither (bit J0). The prescaler divides the mas-
ter oscillator frequency by 2x where x can be from 0 to 8.
Any prescaler value entered that is greater than 8
decodes as 8. The dither applied to the output is con-
trolled with bit J0. When J0 is high, 2% peak dither is
selected. When J0 is low, 4% peak dither is selected.
DAC HIGH/DAC LOW Register
The 2-byte DAC register sets the frequency of the master
oscillator to a particular value within the current offset
range. Each step of the DAC changes the master oscilla-
tor frequency by 10kHz. The first byte is the MSB (DAC
HIGH) and the second byte is the LSB (DAC LOW).
OFFSET Register
The OFFSET register determines the range of frequencies
that can be obtained for a given DAC setting. The factory
default offset is copied into the RANGE register so the
user can access the default offset after making changes
to the OFFSET register. See Table 2 for OFFSET ranges.
Correct operation of the device is not guaranteed out-
side the range 66MHz to 133MHz.
fOUTPUT
MIN FREQUENCY OF SELECTED OFFSET RANGE
DAC VALUE
kHz STEP SIZE
PRESCALER
(
)
(
)
=
+× 10
SDA
SCL
2-WIRE
INTERFACE
VCC
DAC
OFFSET
EEPROM CONTROL
REGISTERS
PRESCALER
ADDR
RANGE
SPRD
PDN
OUT
OE
DAC
TRIANGLE WAVE
GENERATOR
VOLTAGE-CONTROLLED
OSCILLATOR
PRESCALER
BY 1, 2, 4...256
GND
MASTER
OSCILLATOR
OUTPUT
DITHER SIGNAL
DITHER
CONTROL
FREQUENCY
CONTROL VOLTAGE
DS1086
Figure 3. DS1086 Block Diagram
(1)
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