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参数资料
| 型号： | DS1216E |
| 厂商： | DALLAS SEMICONDUCTOR |
| 元件分类： | XO, clock |
| 英文描述： | SmartWatch/RAM 16K/66K(16K/66K带实时时钟的ROM或掉电保护RAM插座) |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, PDIP28 |
| 封装： | 0.600 INCH, DIP-28 |
| 文件页数： | 2/9页 |
| 文件大小： | 91K |
| 代理商： | DS1216E |
DS1216E
031998 2/9
OPERATION
A highly structured sequence of 64 cycles is used to gain
access to time information and temporarily disconnects
the mated memory from the system bus. Information
transfer into and out of the SmartWatch is achieved by
using address bits A0 and A2, control signals OE and CE,
and data I/O line DQ0. All SmartWatch data transfers are
accomplished by executing read cycles to the mated
memory address space. Write and read functions are de-
termined by the level of address bit A2. When address bit
A2 is low, a write cycle is enabled and data must be input
on address bit A0. When address bit A2 is high, a read
cycle is enabled and data is output on data I/O line DQ0.
Either control signal (OE or CE) must transition low to be-
gin and high to end memory cycles that are directed to the
SmartWatch. However, both control signals must be in
an active state during a memory cycle.
Communication with the SmartWatch is established by
pattern recognition of a serial bit stream of 64 bits which
must be matched by executing 64 consecutive write
cycles, placing address bit A2 low with the proper data
on address bit A0. The 64 write cycles are used only to
gain access to the SmartWatch. Prior to executing the
first of 64 write cycles, a read cycle should be executed
by holding A2 high. The read cycle will reset the com-
parison register pointer within the SmartWatch, ensur-
ing the pattern recognition starts with the first bit of the
sequence. When the first write cycle is executed, it is
compared to bit 0 of the 64–bit comparison register. If a
match is found, the pointer increments to the next loca-
tion of the comparison register and awaits the next write
cycle. If a match is not found, the pointer does not ad-
vance and all subsequent write cycles are ignored. If a
read cycle occurs at any time during pattern recognition,
the present sequence is aborted and the comparison
register pointer is reset. Pattern recognition continues
for a total of 64 write cycles as described above, until all
the bits in the comparison register have been matched
(this bit pattern is shown in Figure 1). With a correct
match for 64 bits, the SmartWatch is enabled and data
transfer to or from the timekeeping registers may pro-
ceed. The next 64 cycles will cause the SmartWatch to
either receive data on Data In (A0) or transmit data on
Data Out (DQ0), depending on the level of READ/
WRITE (A2). Cycles to other locations outside the
memory block can be interleaved with CE and OE
cycles without interrupting the pattern recognition se-
quence or data transfer sequence to the SmartWatch.
An unconditional reset to the SmartWatch occurs by ei-
ther bringing A14 (RESET) low if enabled, or on pow-
er–up. The RESET can occur during pattern recogni-
tion or while accessing the SmartWatch registers.
RESET causes access to abort and forces the compari-
son register pointer back to Bit 0 without changing
registers.
NONVOLATILE CONTROLLER OPERATION
The DS1216E SmartWatch performs circuit functions
required to make the timekeeping function nonvolatile.
First, a switch is provided to direct power from the bat-
tery or V
CC
supply, depending on which voltage is great-
er. The second function provides power–fail detection.
Power–fail detection typically occurs at V
TP
. Finally, the
nonvolatile controller protects the SmartWatch register
contents by ignoring any inputs after power–fail detec-
tion has occurred. Power–fail detection also has the
same effect on data transfer as the RESET input.
FRESHNESS SEAL
Each DS1216E is shipped from Dallas Semiconductor
with its lithium energy source disconnected, insuring full
energy capacity. When V
CC
is first applied at a level
greater than V
TP
, the lithium energy source is enabled
for battery backup operation.
SMARTWATCH REGISTER INFORMATION
The SmartWatch information is contained in eight regis-
ters of eight bits each which are sequentially accessed
one bit at a time after the 64–bit pattern recognition se-
quence has been completed. When updating the
SmartWatch registers, each must be handled in groups
of eight bits. Writing and reading individual bits within a
register could produce erroneous results. These read/
write registers are defined in Figure 2.
Data contained in the SmartWatch registers is in binary
coded decimal format (BCD). Reading and writing the
registers is always accomplished by stepping through
all eight registers, starting with bit 0 of register 0 and
ending with bit 7 of register 7.
AM–PM/12/24 MODE
Bit 7 of the hours register is defined as the 12– or
24–hour mode select bit. When high, the 12–hour mode
is selected. In the 12–hour mode, bit 5 is the AM/PM bit
with logic high being PM. In the 24–hour mode, bit 5 is
the second 10–hour bit (20–23 hours).
相关PDF资料 |
PDF描述 |
|---|---|
| DS1216F | SmartWatch/ROM 64K/256K/1M(64K/256K/1M位带实时时钟的ROM或掉电保护RAM插座) |
| DS1218 | Nonvolatile Controller(非易失性控制器) |
| DS1220AB | 16K Nonvolatile SRAM(16K非易失性SRAM) |
| DS1220AD | 16K Nonvolatile SRAM(16K非易失性SRAM) |
| DS1220Y | 16K Nonvolatile SRAM(16K 非易失性静态RAM) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1216F | 功能描述:IC SMART/ROM 3V 64/256/1M 32DIP RoHS:否 类别:集成电路 (IC) >> 存储器 - 控制器 系列:- 标准包装:45 系列:- 控制器类型:静态 RAM（SRAM） 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC W 包装:管件 |
| DS1216F-3 | 功能描述:IC SMART/ROM 3V 64/256/1M 32DIP RoHS:否 类别:集成电路 (IC) >> 存储器 - 控制器 系列:- 标准包装:45 系列:- 控制器类型:静态 RAM（SRAM） 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC W 包装:管件 |
| DS1216H | 功能描述:存储器控制器 SmartWatch RAM RoHS:否 制造商:Maxim Integrated |
| DS1216MP000 | 制造商:Thomas & Betts 功能描述:100A,PLG,2P3W,MG,216,208V |
| DS1216MR000 | 制造商:Thomas & Betts 功能描述:100A,NLT,2P3W,MG,216,208V |
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