参数资料
型号: DS1220AB-100+
厂商: Maxim Integrated Products
文件页数: 6/8页
文件大小: 0K
描述: IC NVSRAM 16KBIT 100NS 24DIP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 14
格式 - 存储器: RAM
存储器类型: NVSRAM(非易失 SRAM)
存储容量: 16K (2K x 8)
速度: 100ns
接口: 并联
电源电压: 4.75 V ~ 5.25 V
工作温度: 0°C ~ 70°C
封装/外壳: 24-DIP 模块(0.600",15.24mm)
供应商设备封装: 24-EDIP
包装: 管件
DS1220AB/AD
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
(T A : See N ote  10)
PARAMETER
V CC Fail Detect to CE and WE Inactive
SYMBOL
t PD
MIN
TYP
MAX
1.5
UNITS
μ s
NOTES
11
V CC slew from V TP to 0V
V CC slew from 0V to V TP
V CC Valid to CE and WE Inactive
V CC Valid to End of Write Protection
t F
t R
t PU
t REC
300
300
2
125
μ s
μ s
ms
ms
(T A = +25°C )
PARAMETER
SYMBOL MIN TYP
MAX UNITS
NOTES
Expected Data Retention Time
t DR
10
years
9
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in the
battery backup mode.
NOTES:
1. W E is high for a read cycle.
2. OE = V IH or V IL . If OE = V IH during write cycle, the output buffers remain in a high-impedance state.
3. t WP is specified as the logical AND of CE and WE . t WP is measured from the latter of CE or CE
going low to the earlier of CE or WE going high.
4. t DS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition, the output
buffers remain in a high-impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high-impedance state during this period.
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