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参数资料
| 型号： | DS1220AB-120+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 2/8页 |
| 文件大小： | 0K |
| 描述： | IC NVSRAM 16KBIT 120NS 24DIP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 14 |
| 格式 - 存储器： | RAM |
| 存储器类型： | NVSRAM（非易失 SRAM） |
| 存储容量： | 16K (2K x 8) |
| 速度： | 120ns |
| 接口： | 并联 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 24-DIP 模块（0.600"，15.24mm） |
| 供应商设备封装： | 24-EDIP |
| 包装： | 管件 |
DS1220AB/AD
READ MODE
The DS1220AB and DS1220AD execute a read cycle whenever WE (Write Enable) is inactive (high) and
CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 11
address inputs (A0-A10) defines which of the 2048 bytes of data is to be accessed. Valid data will be
available to the eight data output drivers within t ACC (Access Time) after the last address input signal is
stable, providing that the CE and OE access times are also satisfied. If CE and OE access times are not
satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is
either t CO for CE or t OE for OE rather than address access.
WRITE MODE
The DS1220AB and DS1220AD execute a write cycle whenever the WE and CE signals are active (low)
after address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of
the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs
must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery
time (t WR ) before another cycle can be initiated. The OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE
active) then WE will disable the outputs in t ODW from its falling edge.
DATA RETENTION MODE
The DS1220AB provides full functional capability for V CC greater than 4.75 volts and write protects by
4.5V. The DS1220AD provides full functional capability for V CC greater than 4.5 volts and write protects
by 4.25V. Data is maintained in the absence of V CC without any additional support circuitry. The
nonvolatile static RAMs constantly monitor V CC . Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high
impedance. As V CC falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when V CC rises above approximately 3.0 volts,
the power switching circuit connects external V CC to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V CC exceeds 4.75 volts for the DS1220AB and 4.5 volts for the
DS1220AD.
FRESHNESS SEAL
Each DS1220 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When V CC is first applied at a level of greater than V TP , the lithium
energy source is enabled for battery backup operation.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1220AB-120+ | 功能描述:NVRAM 16k Nonvolatile SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1220AB-120-IND | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:16k Nonvolatile SRAM |
| ds1220ab150 | 制造商:Maxim Integrated Products 功能描述: |
| DS1220AB-150 | 功能描述:NVRAM 16k Nonvolatile SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1220AB150+ | 制造商:Maxim Integrated Products 功能描述:Nonvolatile RAM,DS1220AB150 2kx8bit 16kb |
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