参数资料
型号: DS1236S-10+T&R
厂商: Maxim Integrated Products
文件页数: 4/19页
文件大小: 0K
描述: IC MICROMANAGER 10% 16-SOIC
标准包装: 1,000
系列: MicroManager
类型: 备用电池电路
监视电压数目: 1
输出: 开路漏极,推挽式
复位: 高有效/低有效
复位超时: 最小为 25 ms
电压 - 阀值: 4.37V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 带卷 (TR)
DS1236
NON-MASKABLE INTERRUPT
The DS1236 generates a non-maskable interrupt NMI for early warning of power failure to a
microprocessor. A precision comparator monitors the voltage level at the IN pin relative to a reference
generated by the internal band gap. The IN pin is a high-impedance input allowing for a user-defined
sense point. An external resistor voltage divider network (Figure 6) is used to interface with high voltage
signals. This sense point may be derived from the regulated 5-volt supply or from a higher DC voltage
level closer to the main system power input. Since the IN trip point V TP is 2.54 volts, the proper values
for R1 and R2 can be determined by the equation as shown in Figure 6. Proper operation of the DS1236
requires that the voltage at the IN pin be limited to V IN . Therefore, the maximum allowable voltage at the
supply being monitored (V MAX ) can also be derived as shown in Figure 6. A simple approach to solving
this equation is to select a value for R2 high enough to keep power consumption low, and solve for R1.
The flexibility of the IN input pin allows for detection of power loss at the earliest point in a power
supply system, maximizing the amount of time for microprocessor shutdown between NMI and RST or
RST .
When the supply being monitored decays to the voltage sense point, the DS1236 pulses the NMI output
to the active state for a minimum of 200 μ s. The NMI power-fail detection circuitry also has built-in time
domain hysteresis. That is, the monitored supply is sampled periodically at a rate determined by an
internal ring oscillator running at approximately 30 kHz (33 μ s/cycle). Three consecutive samplings of
out-of-tolerance supply (below V SENSE ) must occur at the IN pin to activate NMI . Therefore, the supply
must be below the voltage sense point for approximately 100 μ s or the comparator will reset. In this way,
power supply noise is removed from the monitoring function, preventing false trips. During a power-up,
any IN pin levels below V TP are disabled from reaching the NMI pin until V CC rises to V CCTP . As a result,
any potential NMI pulse will not be initiated until V CC reaches V CCTP .
Removal of an active low level on the NMI pin is controlled by either an internal time-out (when IN pin
is less than V TP ) or by the subsequent rise of the IN pin above V TP . The initiation and removal of the NMI
signal during power-up results in an NMI pulse of from 0 μ s minimum to 500 μ s maximum, depending
on the relative voltage relationship between V CC and the IN pin voltage. As an example, when the IN pin
is tied to ground during power-up, the internal time-out will result in a pulse of 200 μ s minimum to 500
μ s maximum. In contrast, if the IN pin is tied to V CCO during power-up, NMI will not produce a pulse on
power-up. Note that a fast slewing power supply may cause the NMI to be virtually nonexistent on
power-up. This is of no consequence, however, since an RST will be active.
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