参数资料
型号: DS1238A-10N
厂商: Maxim Integrated Products
文件页数: 2/14页
文件大小: 0K
描述: IC MICROMANAGER 10% IND 16-DIP
标准包装: 25
系列: MicroManager
类型: 备用电池电路
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 高有效/低有效
复位超时: 最小为 40 ms
电压 - 阀值: 4.37V
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 16-DIP(0.300",7.62mm)
供应商设备封装: 16-PDIP
包装: 管件
DS1238
debounce circuit connected to the RST pin. An internal watchdog timer can also force the reset outputs to
the active state if the strobe input is not driven low prior to watchdog timeout. Oscillator control pins
OSCSEL and OSCIN provide either external or internal clock timing for both the reset pulse width and
the watchdog timeout period. The Watchdog Status and Reset Voltage Threshold are provided via WDS
and RVT , respectively. A block diagram of the DS1238 is shown in Figure 1.
PIN DESCRIPTION
PIN NAME
V BAT
V CCO
V CC
GND
PF
RVT
OSCIN
OSCSEL
IN
NMI
ST
CEO
CEI
WDS
RST
RST
DESCRIPTION
+3V battery input provides nonvolatile operation of control functions.
V CC output for nonvolatile SRAM applications.
+5V primary power input.
System ground.
Power-fail indicator, active high, used for external power switching as shown in
Figure 9.
Reset Voltage Threshold. Indicates that V CC is below the reset voltage threshold.
Oscillator input or timing capacitor. See Table 1.
Oscillator Select. Selects internal or external clock functions. See Table 1.
Early warning power-fail input. This voltage sense point can be tied (via resistor
divider) to a user-selected voltage.
Non-maskable interrupt. Used in conjunction with the IN pin to indicate an impending
power failure.
Strobe input. A high-to-low transition will reset the watchdog timer, indicating that
software is still in control.
Chip enable output. Write protected. Used with nonvolatile SRAM applications.
Chip enable input.
Watchdog Status. Indicates that a watchdog timeout has occurred.
Active low reset output.
Active high reset output.
POWER MONITOR
The DS1238 employs a band gap voltage reference and a precision comparator to monitor the 5-volt
supply (V CC ) in microprocessor-based systems. When an out-of-tolerance condition occurs, the RVT ,
RST, and RST outputs are driven to the active state. The V CC trip point (V CCTP ) is set for 10% operation
so that the RVT , RST and RST outputs will become active as V CC falls below 4.5 volts (4.37 typical).
The V CCTP for the 5% operation option (DS1238-5) is set for 4.75 volts (4.62 typical). The RST and RST
signals are excellent for microprocessor reset control, as processing is stopped at the last possible moment
of in-tolerance V CC . On power up, RVT will become inactive as soon as V CC rises above V CCTP . However,
the RST and RST signals remain active for a minimum of 50 ms (100 ms typical) after V CCTP is reached
to allow the power supply and microprocessor to stabilize.
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