- 您现在的位置：买卖IC网 > PDF目录9402 > DS1244Y-70+ (Maxim Integrated Products)IC NVSRAM 256KBIT 70NS 28DIP PDF资料下载
参数资料
| 型号： | DS1244Y-70+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 16/20页 |
| 文件大小： | 0K |
| 描述： | IC NVSRAM 256KBIT 70NS 28DIP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 12 |
| 类型： | Phantom 计时芯片 |
| 特点： | 闰年，NVSRAM |
| 存储容量： | 32KB |
| 时间格式： | HH:MM:SS:hh（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 28-DIP 模块（0.600"，15.24mm） |
| 供应商设备封装： | 28-EDIP |
| 包装： | 管件 |
| 产品目录页面： | 1432 (CN2011-ZH PDF) |
DS1244/DS1244P
5 of 20
DATA RETENTION MODE
The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF.
However, when VCC is below the power fail point, VPF (point at which write protection occurs), the
internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch
point, VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC
operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.
The 3.3V device is fully accessible and data can be written or read only when VCC is greater than VPF.
When VCC fall as below the VPF, access to the device is inhibited. If VPF is less than VBAT, the device
power is switched from VCC to the backup supply (VBAT ) when VCC drops below VPF. If VPF is greater
than VBAT, the device power is switched from VCC to the backup supply (VBAT ) when VCC drops below
VBAT. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal
levels.
All control, data, and address signals must be powered down when VCC is powered down.
PHANTOM CLOCK OPERATION
Communication with the phantom clock is established by pattern recognition on a serial bit stream of
64 bits, which must be matched by executing 64 consecutive write cycles containing the proper data on
DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the
phantom clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of the chip enable, output enable, and write enable. Initially, a read cycle to any memory location using
the CE and OE control of the phantom clock starts the pattern recognition sequence by moving a pointer
to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the
CE
and WE control of the SmartWatch. These 64 write cycles are used only to gain access to the
phantom clock. Therefore, any address to the memory in the socket is acceptable. However, the write
cycles generated to gain access to the phantom clock are also writing data to a location in the mated
RAM. The preferred way to manage this requirement is to set aside just one address location in RAM as a
phantom clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64-bit
comparison register. If a match is found, the pointer increments to the next location of the comparison
register and awaits the next write cycle. If a match is not found, the pointer does not advance and all
subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the
present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for
a total of 64 write cycles as described above until all the bits in the comparison register have been
matched (Figure 1). With a correct match for 64 bits, the phantom clock is enabled and data transfer to or
from the timekeeping registers can proceed. The next 64 cycles will cause the phantom clock to either
receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to other
locations outside the memory block can be interleaved with CE cycles without interrupting the pattern
recognition sequence or data transfer sequence to the phantom clock.
相关PDF资料 |
PDF描述 |
|---|---|
| VI-23Y-MY-F2 | CONVERTER MOD DC/DC 3.3V 33W |
| VE-J4M-MZ | CONVERTER MOD DC/DC 10V 25W |
| DS1511Y+ | IC RTC WDOG Y2K 5V 28-EDIP |
| VI-23Y-MY-F1 | CONVERTER MOD DC/DC 3.3V 33W |
| VE-J4L-MZ | CONVERTER MOD DC/DC 28V 25W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1244Y-70+ | 功能描述:实时时钟 256k NV SRAM w/Phantom Clock RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| DS1244YP/WP | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:PowerCap with Crystal |
| DS1244YP-70 | 功能描述:IC NVSRAM 256KBIT 70NS 34PCM RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 实时时钟 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- 类型:时钟/日历 特点:警报器，闰年，SRAM 存储容量:- 时间格式:HH:MM:SS（12/24 小时） 数据格式:YY-MM-DD-dd 接口:SPI 电源电压:2 V ~ 5.5 V 电压 - 电源，电池:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WDFN 裸露焊盘 供应商设备封装:8-TDFN EP 包装:管件 |
| DS1244YP-70+ | 功能描述:实时时钟 256k NV SRAM w/Phantom Clock RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| DS-1244ZJ | 制造商:Hikvision USA 功能描述:DOME CAM CEILING TRIM BRACKET4.75IN X .95IN 制造商:HIKVISION 功能描述:DOME CAM CEILING TRIM BRACKET 4.75IN X .95IN |
发布紧急采购，3分钟左右您将得到回复。