参数资料
型号: DS1244Y-70
英文描述: 256k NV SRAM with Phantom Clock
中文描述: 256k非易失SRAM与幻影时钟
文件页数: 10/19页
文件大小: 292K
代理商: DS1244Y-70
ADS1244
SBAS273
10
www.ti.com
POWER-UP
Self-calibration is performed at power-up to minimize offset and
gain errors. In order for the self-calibration at power-up to work
properly, make sure that both AVDD and DVDD increase
monotonically and are settled by t
1
, as shown in Figure 11.
SCLK must be held LOW during this time. Once calibration is
complete,
DRDY/DOUT
will go LOW indicating data is ready
for retrieval. The time required before the first data is ready (t
6
)
depends on how fast AVDD and DVDD ramp to their final value
(t
1
). For most ramp rates, t
1
+ t
2
350ms (f
CLK
= 2.4576MHz).
If the system environment is not stable during power-up (the
temperature is varying or the supply voltages are moving
around), it is recommended that a self-calibration be issued
after everything is stable.
DATA FORMAT
The ADS1244 outputs 24 bits of data in Binary Two
s
Complement format. The Least Significant Bit (LSB) has a
weight of (2V
REF
)/(2
23
1). A positive full-scale input pro-
FIGURE 11. Power-Up Timing.
AVDD and DVDD
DRDY/DOUT
SCLK
t
1
t
2
Data ready after power-up calibration.
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
t
1(1)
t
2(1)
AVDD and DVDD settling time.
Wait time for calibration and first data conversion.
100
ms
ms
316
NOTE: (1) Values given for f
CLK
= 2.4576MHz. For different CLK frequencies, scale proportional
to CLK period.
duces an output code of 7FFFFF
H
and the negative full-scale
input produces an output code of 800000
H
. The output clips
at these codes for signals exceeding full-scale. Table I
summarizes the ideal output codes for different input signals.
INPUT SIGNAL V
IN
(AINP
AINN)
+2V
REF
+
2
2
0
2
2
IDEAL OUTPUT CODE
(1)
7FFFFF
H
1
23
V
REF
000001
H
000000
H
1
23
V
REF
FFFFFF
H
2
2
23
2
1
23
V
REF
800000
H
NOTE: (1) Excludes effects of noise, INL, offset, and gain errors.
TABLE I. Ideal Output Code versus Input Signal.
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