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| 型号： | DS1248YP-70+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 14/19页 |
| 文件大小： | 0K |
| 描述： | IC NVSRAM 1MBIT 70NS 34PCM |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 40 |
| 类型： | Phantom 计时芯片 |
| 特点： | NVSRAM |
| 存储容量： | 128KB |
| 时间格式： | HH:MM:SS:hh（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电压 - 电源，电池： | 3V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 34-PowerCap? 模块 |
| 供应商设备封装： | 34-PowerCap 模块 |
| 包装： | 管件 |
| 产品目录页面： | 1432 (CN2011-ZH PDF) |
DS1248/DS1248P 1024K NV SRAM with Phantom Clock
4 of 19
RAM READ MODE
The DS1248 executes a read cycle whenever WE (write enable) is inactive (high) and CE (chip enable) is
active (low). The unique address specified by the 17 address inputs (A0–A16) defines which of the 128k
bytes of data is to be accessed. Valid data will be available to the eight data-output drivers within tACC
(access time) after the last address input signal is stable, providing that CE and OE (output enable) access
times and states are also satisfied. If OE and CE access times are not satisfied, then data access must be
measured from the later occurring signal (CE or OE) and the limiting parameter is either tCO for CE or tOE
for OE, rather than address access.
RAM WRITE MODE
The DS1248 is in the write mode whenever the WE and CE signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CEor WE. All address inputs must
be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output bus has been enabled (CE and OE active)
then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF.
However, when VCC is below the power-fail point, VPF (point at which write protection occurs), the
internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch
point, VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC
operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.
The 3.3V device is fully accessible and data can be written or read only when VCC is greater than VPF.
When VCC falls below VPF, access to the device is inhibited. If VPF is less than VBAT, the device power is
switched from VCC to the backup supply (VBAT) when VCC drops below VPF. If VPF is greater than VBAT,
the device power is switched from VCC to the backup supply (VBAT) when VCC drops below VBAT. RTC
operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.
All control, data, and address signals must be powered down when VCC is powered-down.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1248YP-70+ | 功能描述:实时时钟 1024k NV SRAM w/Phantom Clock RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| DS1248YP70IND | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:1024k NV SRAM with Phantom Clock |
| DS1249AB | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:2048k Nonvolatile SRAM |
| DS1249AB100 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:2048k Nonvolatile SRAM |
| DS1249AB-100 | 功能描述:NVRAM 2048K NV SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
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