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参数资料
| 型号： | DS1250W-100IND+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 2/9页 |
| 文件大小： | 0K |
| 描述： | IC NVSRAM 4MBIT 100NS 32DIP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 11 |
| 格式 - 存储器： | RAM |
| 存储器类型： | NVSRAM（非易失 SRAM） |
| 存储容量： | 4M (512K x 8) |
| 速度： | 100ns |
| 接口： | 并联 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-DIP 模块（0.600"，15.24mm） |
| 供应商设备封装： | 32-EDIP |
| 包装： | 管件 |
DS1250W
DESCRIPTION
The DS1250W 3.3V 4096k Nonvolatile SRAM is a 4,194,304-bit, fully static, nonvolatile SRAM
organized as 524,288 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and
control circuitry, which constantly monitors V CC for an out-of-tolerance condition. When such a condition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. DIP-package DS1250W devices can be used in place of existing 512k
x 8 static RAMs directly conforming to the popular bytewide 32-pin DIP standard. DS1250W devices in
the PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC
PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write
cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
READ MODE
The DS1250W executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 19 address inputs
(A 0 - A 18 ) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within t ACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal ( CE or OE ) and the limiting
parameter is either t CO for CE or t OE for OE rather than address access.
WRITE MODE
The DS1250W executes a write cycle whenever the WE a nd CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t WR )
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE
will disable the outputs in t ODW from its falling edge.
DATA RETENTION MODE
The DS1250W provides full functional capability for V CC greater than 3.0 volts and write protects by 2.8
volts. Data is maintained in the absence of V CC without any additional support circuitry. The nonvolatile
static RAMs constantly monitor V CC . Should the supply voltage decay, the NV SRAMs automatically
write protect themselves, all inputs become “don’t care,” and all outputs become high-impedance. As V CC
falls below approximately 2.5 volts, a power switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when V CC rises above approximately 2.5 volts, the power
switching circuit connects external V CC to RAM and disconnects the lithium energy source. Normal
RAM operation can resume after V CC exceeds 3.0 volts.
FRESHNESS SEAL
Each DS1250W device is shipped from Maxim with its lithium energy source disconnected, guaranteeing
full energy capacity. When V CC is first applied at a level greater than 3.0 volts, the lithium energy source
is enabled for battery back-up operation.
PACKAGES
The DS1250W is available in two packages: 32-pin DIP and 34-pin PowerCap Module (PCM). The 32-
pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a single
package with a JEDEC-standard 600-mil DIP pinout. The 34-pin PowerCap Module integrates SRAM
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相关PDF资料 |
PDF描述 |
|---|---|
| DS1350YP-100+ | IC NVSRAM 4MBIT 100NS 34PCM |
| DS1350ABP-100+ | IC NVSRAM 4MBIT 100NS 34PCM |
| DS1250AB-100IND+ | IC NVSRAM 4096KBIT 100NS 32DIP |
| DS1250Y-100IND+ | IC NVSRAM 4MBIT 100NS 32DIP |
| DS1250YP-70IND+ | IC NVSRAM 4MBIT 70NS 34PCM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1250W-100IND+ | 功能描述:NVRAM 3.3V 4096K NV SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1250W-150 | 功能描述:NVRAM 3.3V 4096K NV SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1250W-150+ | 功能描述:NVRAM 3.3V 4096K NV SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1250W-150-IND | 制造商:未知厂家 制造商全称:未知厂家 功能描述:NVRAM (Battery Based) |
| DS1250WP-100 | 功能描述:NVRAM 3.3V 4096K NV SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
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