DS1251/DS1251P
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PIN DESCRIPTION (continued)
PIN
NAME
FUNCTION
EDIP
PowerCap
22
8
CE
Active-Low Chip-Enable Input
24
7
OE
Active-Low Output-Enable Input
29
6
WE
Active-Low Write-Enable Input
32
5
VCC
Power-Supply Input
—
4
N.C.
No Connection
16
17
GND
Ground
DESCRIPTION
The DS1251 4096K NV SRAM with Phantom Clock is a fully static nonvolatile RAM (organized as
512K words by 8 bits) with a built-in real-time clock. The DS1251Y has a self-contained lithium energy
source and control circuitry, which constantly monitors VCC for an out-of-tolerance condition. When such
a condition occurs, the lithium energy source is automatically switched on and write protection is
unconditionally enabled to prevent garbled data in both the memory and real-time clock.
The phantom clock provides timekeeping information including hundredths of seconds, seconds, minutes,
hours, days, dates, months, and years. The date at the end of the month is automatically adjusted for
months with fewer than 31 days, including correction for leap years. The phantom clock operates in either
24-hour or 12-hour format with an AM/PM indicator.
PACKAGES
The DS1251 is available in two packages: 32-pin DIP and 34-pin PowerCap module. The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon in one package. The 34-pin
PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1251P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery because of the high temperatures required for
solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and
PowerCap are ordered separately and shipped in separate containers.
RAM READ MODE
The DS1251 executes a read cycle whenever WE (write enable) is inactive (high) and CE (chip enable) is
active (low). The unique address specified by the 19 address inputs (A0–A18) defines which of the 512K
bytes of data is to be accessed. Valid data will be available to the eight data-output drivers within tACC
(access time) after the last address input signal is stable, providing that CE and OE (output enable) access
times and states are also satisfied. If OE and CE access times are not satisfied, then data access must be
measured from the later occurring signal ( CE or OE ) and the limiting parameter is either tCO for CE or
tOE for OE , rather than address access.
RAM WRITE MODE
The DS1251 is in the write mode whenever the WE and CE signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must