参数资料
型号: DS12885S
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: Timer or RTC
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO24
封装: 0.300 INCH, SOIC-24
文件页数: 21/22页
文件大小: 356K
代理商: DS12885S
DS12885/DS12887/DS12887A/DS12C887/DS12C887A
Real-Time Clock
8
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Pin Description
PIN
SO,
PDIP
EDIP
PLCC
TQFP
NAME
FUNCTION
1
2
29
MOT
Motorola or Intel Bus Timing Selector. This pin selects one of two bus types. When
connected to VCC, Motorola bus timing is selected. When connected to GND or
left disconnected, Intel bus timing is selected. The pin has an internal pulldown
resistor.
2—
3
30
X1
3—
4
31
X2
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator
circuitry is designed for operation with a crystal having a 6pF specified load
capacitance (CL). Pin X1 is the input to the oscillator and can optionally be
connected to an external 32.768kHz oscillator. The output of the internal oscillator,
pin X2, is floated if an external oscillator is connected to pin X1.
4–11
5–10,
12, 14
1, 2, 3,
5, 7, 8,
9, 11
AD0–
AD7
Multiplexed, Bidirectional Address/Data Bus. The addresses are presented during
the first portion of the bus cycle and latched into the device by the falling edge of
AS. Write data is latched by the falling edge of DS (Motorola timing) or the rising
edge of R/W (Intel timing). In a read cycle, the device outputs data during the
latter portion of DS (DS and R/W high for Motorola timing, DS low and R/W high for
Intel timing). The read cycle is terminated and the bus returns to a high-
impedance state as DS transitions low in the case of Motorola timing or as DS
transitions high in the case of Intel timing.
12, 16
12
15, 20
12, 17
GND
Ground
13
16
13
CS
Active-Low Chip-Select Input. The chip-select signal must be asserted low for a
bus cycle in the device to be accessed. CS must be kept in the active state during
DS and AS for Motorola timing and during DS and R/W for Intel timing. Bus cycles
that take place without asserting CS will latch addresses, but no access occurs.
When VCC is below VPF volts, the device inhibits access by internally disabling the
CS input. This action protects the RTC data and the RAM data during power
outages.
14
17
14
AS
Address Strobe Input. A positive-going address-strobe pulse serves to
demultiplex the bus. The falling edge of AS causes the address to be latched
within the device. The next rising edge that occurs on the AS bus clears the
address regardless of whether CS is asserted. An address strobe must
immediately precede each write or read access. If a write or read is performed
with CS deasserted, another address strobe must be performed prior to a read or
write access with CS asserted.
15
19
16
R/W
Read/Write Input. The R/W pin has two modes of operation. When the MOT pin is
connected to VCC for Motorola timing, R/W is at a level that indicates whether the
current cycle is a read or write. A read cycle is indicated with a high level on R/W
while DS is high. A write cycle is indicated when R/W is low during DS. When the
MOT pin is connected to GND for Intel timing, the R/W signal is an active-low
signal. In this mode, the R/W pin operates in a similar fashion as the write-enable
signal (WE) on generic RAMs. Data are latched on the rising edge of the signal.
相关PDF资料
PDF描述
DS12885QN 1 TIMER(S), REAL TIME CLOCK, PQCC28
DS12C887 1 TIMER(S), REAL TIME CLOCK, PDIP24
DS12887 1 TIMER(S), REAL TIME CLOCK, PDIP24
DS1302S 0 TIMER(S), REAL TIME CLOCK, PDSO8
DS1302N 0 TIMER(S), REAL TIME CLOCK, PDIP8
相关代理商/技术参数
参数描述
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