D
RTC with Constant-Voltage Trickle Charger
____________________________________________________________________
11
Pin Description (continued)
PIN
EDIP
SO
BGA
NAME
FUNCTION
18
18
A2
RESET
Reset Input. The
RESET
pin has no effect on the clock, calendar, or RAM. On power-up,
the
RESET
pin can be held low for a time to allow the power supply to stabilize. The
amount of time that
RESET
is held low is dependent on the application. However, if
RESET
is used on power-up, the time
RESET
is low should exceed 200ms to ensure that the
internal timer that controls the DS12R885 on power-up has timed out. When
RESET
is low
and V
CC
is above V
PF
, the following occurs:
A. Periodic interrupt-enable (PIE) bit is cleared to 0.
B. Alarm interrupt-enable (AIE) bit is cleared to 0.
C. Update-ended interrupt-enable (UIE) bit is cleared to 0.
D. Periodic-interrupt flag (PF) bit is cleared to 0.
E. Alarm-interrupt flag (AF) bit is cleared to 0.
F. Update-ended interrupt flag (UF) bit is cleared to 0.
G. Interrupt-request status flag (IRQF) bit is cleared to 0.
H.
IRQ
pin is in the high-impedance state.
I. The device is not accessible until
RESET
is returned high.
J. Square-wave output-enable (SQWE) bit is cleared to 0.
In a typical application,
RESET
can be connected to V
CC
. This connection allows the
DS12R885 to go in and out of power fail without affecting any of the control registers.
19
19
A4
IRQ
Interrupt Request Output. The
IRQ
pin is an active-low output of the DS12R885 that can be
used as an interrupt input to a processor. The
IRQ
output remains low as long as the
status bit causing the interrupt is present and the corresponding interrupt-enable bit is set.
The processor program normally reads the C register to clear the
IRQ
pin. The
RESET
pin
also clears pending interrupts. When no interrupt conditions are present, the
IRQ
level is in
the high-impedance state. Multiple interrupting devices can be connected to an
IRQ
bus,
provided that they are all open drain. The
IRQ
pin is an open-drain output and requires an
external pullup resistor to V
CC
.
20
—
—
V
BACKUP
Connection for Rechargeable Battery or Super Cap. This pin provides trickle charging
when V
CC
is greater than V
BACKUP
.
21
—
A5
RCLR
RAM Clear. The active-low
RCLR
pin is used to clear (set to logic 1) all 114 bytes of
general-purpose RAM, but does not affect the RAM associated with the RTC. To clear the
RAM,
RCLR
must be forced to an input logic 0 during battery-backup mode when V
CC
is
not applied. The
RCLR
function is designed to be used through a human interface
(shorting to ground manually or by a switch) and not to be driven with external buffers.
This pin is internally pulled up. Do not use an external pullup resistor on this pin.
23
23
C4
SQW
Square-Wave Output. The SQW pin can output a signal from one of 13 taps provided by
the 15 internal divider stages of the RTC. The frequency of the SQW pin can be changed
by programming Register A, as shown in Table 1. The SQW signal can be turned on and
off using the SQWE bit in Register B. The SQW signal is not available when V
CC
is less
than V
PF
.
24
24
A6–A8,
B1–B8,
C6–C8
V
CC
DC Power Pin for Primary Power Supply. When V
CC
is applied within normal limits, the
device is fully accessible and data can be written and read. When V
CC
is below V
PF
reads
and writes are inhibited.