参数资料
型号: DS1315-5
厂商: Maxim Integrated Products
文件页数: 18/21页
文件大小: 0K
描述: IC TIME CHIP PHANTOM 5V 16-DIP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 25
类型: Phantom 计时芯片
特点: 闰年
时间格式: HH:MM:SS:hh(12/24 小时)
数据格式: YY-MM-DD-dd
接口: 并联
电源电压: 4.5 V ~ 5.5 V
电压 - 电源,电池: 2.5 V ~ 3.7 V
工作温度: 0°C ~ 70°C
安装类型: 通孔
封装/外壳: 16-DIP(0.300",7.62mm)
供应商设备封装: 16-PDIP
包装: 管件
其它名称: DS13155
DS1315 Phantom Time Chip
6 of 21
Nonvolatile Controller Operation
The operation of the nonvolatile controller circuits within the Time Chip is determined by the level of the
ROM/ RAM select pin. When ROM/ RAM is connected to ground, the controller is set in the RAM mode
and performs the circuit functions required to make CMOS RAM and the timekeeping function
nonvolatile. A switch is provided to direct power from the battery inputs or VCCI to VCCO with a
maximum voltage drop of 0.3 volts. The VCCO output pin is used to supply uninterrupted power to CMOS
SRAM. The DS1315 also performs redundant battery control for high reliability. On power-fail, the
battery with the highest voltage is automatically switched to VCCO. If only one battery is used in the
system, the unused battery input should be connected to ground.
The DS1315 safeguards the Time Chip and RAM data by power-fail detection and write protection.
Power-fail detection occurs when VCCI falls below VPF which is set by an internal bandgap reference. The
DS1315 constantly monitors the VCCI supply pin. When VCCI is less than VPF, power-fail circuitry forces
the chip enable output ( CEO ) to VCCI or VBAT-0.2 volts for external RAM write protection. During
nominal supply conditions, CEO will track CEI with a propagation delay. Internally, the DS1315 aborts
any data transfer in progress without changing any of the Time Chip registers and prevents future access
until VCCI exceeds VPF. A typical RAM/Time Chip interface is illustrated in Figure 3.
When the ROM/ RAM pin is connected to VCCO, the controller is set in the ROM mode. Since ROM is a
read-only device that retains data in the absence of power, battery backup and write protection is not
required. As a result, the chip enable logic will force CEO low when power fails. However, the Time
Chip does retain the same internal nonvolatility and write protection as described in the RAM mode. A
typical ROM/Time Chip interface is illustrated in Figure 4.
Figure 3. DS1315-to-RAM/Time Chip Interface
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