参数资料
| 型号： | DS1339AU+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 4/19页 |
| 文件大小： | 0K |
| 描述： | IC RTC I2C W/ALARM 8USOP |
| 标准包装： | 3,000 |
| 类型： | 时钟/日历 |
| 特点： | 警报器，闰年，方波输出，涓流充电器 |
| 时间格式： | HH:MM:SS（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.71 V ~ 5.5 V |
| 电压 - 电源，电池： | 1.3 V ~ 3.7 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-uMAX |
| 包装： | 带卷 (TR) |
DS1339A
Low-Current, I2C, Serial Real-Time Clock
12
Maxim Integrated
Control Register (0Eh)
The control register controls the operation of the SQW/INT pin and provides oscillator status.
Bit 7: Enable Oscillator (EOSC). When the EOSC bit is 0, the oscillator is enabled. When this bit is a 1, the oscillator
is disabled. This bit is cleared (0) when power is first applied.
Bit 5: Battery-Backed Square-Wave Interrupt (BBSQI). When set to logic 1, this bit enables the SQW/INT output
functionality while the part is powered by VBACKUP. When set to logic 0, this bit disables the SQW/INT output while the
part is powered by VBACKUP.
Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the SQW/INT output when the square-
wave has been enabled (INTCN=0). Table 5 lists the square-wave frequencies that can be selected with the RS bits.
Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output pin.
When the INTCN bit is set to logic 1, a match between the timekeeping registers and the Alarm 1 or Alarm 2 registers
activate the SQW/INT pin (provided that the alarm is enabled). When the INTCN bit is set to logic 0, a square wave is
output on the SQW/INT pin. This bit is set to logic 0 when power is first applied.
Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to a logic 1, this bit permits the Alarm 2 Flag (A2F) bit in the status
register to assert SQW/INT (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0, the A2F bit
does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied.
Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the Alarm 1 Flag (A1F) bit in the status
register to assert SQW/INT (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, the A1F bit
does not initiate an interrupt signal. The A1IE bit is disabled (logic 0) when power is first applied.
Table 5. SQW/INT Output
INTCN
RS2
RS1
SQW/INT OUTPUT
A2IE
A1IE
0
1Hz
X
0
1
4.096kHz
X
0
1
0
8.192kHz
X
0
1
32.768kHz
X
1
X
A1F
0
1
X
A2F
1
0
1
X
A2F + A1F
1
Bit #
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Name
EOSC
0
BBSQI
RS2
RS1
INTCN
A2IE
A1IE
POR
0
1
0
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| DS1339BU+T | 制造商:Maxim Integrated Products 功能描述:SERIAL RTC 1.8-3.3V HESR USOP TRL - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC RTC I2C W/ALARM 8UMAX |
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