参数资料
型号: DS1340Z-33+T&R
厂商: Maxim Integrated Products
文件页数: 15/16页
文件大小: 0K
描述: IC RTC I2C W/CHARGER 3.3V 8-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 时钟/日历
特点: 闰年,方波输出,涓流充电器
时间格式: HH:MM:SS(24 小时)
数据格式: YY-MM-DD-dd
接口: I²C,2 线串口
电源电压: 2.97 V ~ 5.5 V
电压 - 电源,电池: 1.3 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
Address Map
Table 3 shows the DS1340 address map. The RTC reg-
isters are located in address locations 00h to 06h, and
the control register is located at 07h. The trickle-charge
and flag registers are located in address locations 08h
to 09h. During a multibyte access of the timekeeping
registers, when the address pointer reaches 07h—the
end of the clock and control register space—it wraps
around to location 00h. Writing the address pointer to
the corresponding location accesses address locations
08h and 09h. After accessing location 09h, the address
pointer wraps around to location 00h. On a I2C START,
STOP, or address pointer incrementing to location 00h,
the current time is transferred to a second set of regis-
ters. The time information is read from these secondary
registers, while the clock may continue to run. This
eliminates the need to reread the registers in case the
main registers update during a read.
Clock and Calendar
The time and calendar information is obtained by read-
ing the appropriate register bytes. Table 3 shows the
RTC registers. The time and calendar data are set or
initialized by writing the appropriate register bytes. The
contents of the time and calendar registers are in the
binary-coded decimal (BCD) format. The day-of-week
I2C RTC with Trickle Charger
8
Maxim Integrated
DS1340
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FUNCTION
RANGE
00H
EOSC
10 Seconds
Seconds
00–59
01H
X
10 Minutes
Minutes
00–59
02H
CEB
CB
10 Hours
Hours
Century/Hours
0–1; 00–23
03H
X
Day
01–07
04H
X
10 Date
Date
01–31
05H
X
10 Month
Month
01–12
06H
10 Year
Year
00–99
07H
OUT
FT
S
CAL4
CAL3
CAL2
CAL1
CAL0
Control
08H
TCS3
TCS2
TCS1
TCS0
DS1
DS0
ROUT1
ROUT0
Trickle Charger
09H
OSF
0
Flag
Table 3. Address Map
X = Read/Write bit
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied.
SERIAL
INTERFACE
AND ADDRESS
REGISTER
CONTROL
LOGIC
"C" VERSION ONLY
SCL
SDA
512Hz
MUX/
BUFFER
FT/OUT
USER BUFFER
(7 BYTES)
CLOCK AND
CALENDAR
REGISTERS
32,768Hz
1Hz
X1
POWER
CONTROL
VCC
VBACKUP
DIVIDER AND
CALIBRATION
CIRCUIT
X2
CL
N
DS1340
Figure 5. Functional Diagram
相关PDF资料
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