参数资料
型号: DS1371U+T&R
厂商: Maxim Integrated Products
文件页数: 4/15页
文件大小: 0K
描述: IC BINARY COUNTER 32-BIT 8-USOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 3,000
类型: 二进制计数器
特点: 警报器,方波输出,监视计时器
时间格式: 二进制
数据格式: 二进制
接口: I²C,2 线串口
电源电压: 1.7 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-uMAX
包装: 带卷 (TR)
DS1371
12 of 15
Data valid: The state of the data line represents valid data when, after a START condition, the
data line is stable for the duration of the high period of the clock signal. The data on the line must
be changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition.
The number of data bytes transferred between the START and the STOP conditions is not limited,
and is determined by the master device. The information is transferred byte-wise and each
receiver acknowledges with a ninth bit. Within the I2C bus specifications a standard mode
(100kHz clock rate) and a fast mode (400kHz clock rate) are defined.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge
after the reception of each byte. The master device must generate an extra clock pulse, which is
associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related
clock pulse. Setup and hold times must be taken into account. A master must signal an end of data
to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the
slave. In this case, the slave must leave the data line HIGH to enable the master to generate the
STOP condition.
Figure 4. I
2C Data Transfer Overview
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