参数资料
型号: DS1374U-3
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 电源管理
英文描述: I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
中文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO10
封装: 3 MM, MICRO, SOP-10
文件页数: 5/15页
文件大小: 616K
代理商: DS1374U-3
D
I
2
C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
_____________________________________________________________________
5
POWER-UP/POWER-DOWN CHARACTERISTICS
(T
A
= -40°C to +85°C) (Figure 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
Detect to Recognize Inputs
(V
CC
Rising)
t
RPU
(Note 23)
250
ms
V
CC
Fall Time; V
PF(MAX)
to
V
PF(MIN)
t
F
300
μs
V
CC
Rise Time; V
PF(MIN)
to
V
PF(MAX)
t
R
0
μs
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when the device is in write protection.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
The
RST
pin has an internal 50k
pullup resistor to V
CC
.
Note 11:
Trickle charger disabled.
Note 12:
I
CCA
—SCL clocking at max frequency = 400kHz.
Note 13:
Specified with I
2
C bus inactive.
Note 14:
Measured with a 32.768kHz crystal attached to the X1 and X2 pins.
Note 15:
WDSTR = 1. BBSQW = 1 is required for operation when V
CC
is below the power-fail trip point (or absent).
Note 16:
C
B
—total capacitance of one bus line in pF.
Note 17:
After this period, the first clock pulse is generated.
Note 18:
The maximum t
HD:DAT
only has to be met if the device does not stretch the low period (t
LOW
) of the SCL signal.
Note 19:
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V
IHMIN
of the SCL sig-
nal) to bridge the undefined region of the falling edge of SCL.
Note 20:
A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
to 250ns must be met. This is
automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low
period of the SCL signal, it must output the next data bit to the SDA line t
R
max + t
SU:DAT
= 1000 + 250 = 1250ns before
the SCL line is released.
Note 21:
Guaranteed by design. Not production tested.
Note 22:
The parameter t
OSF
is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of
0V
V
CC
V
CC MAX
and 1.3V
V
BACKUP
3.7V.
Note 23:
This delay applies only if the oscillator is enabled and running. If the
EOSC
bit is 1, the startup time of the oscillator is
added to this delay.
Limits at -40°C are guaranteed by design and not production tested.
All voltages are referenced to ground.
V
BACKUP
should not exceed V
CC
MAXor 3.7V, whichever is greater.
The use of the 250
trickle-charge resistor is not allowed at V
CC
> 3.63V and should not be enabled.
Measured at V
CC
= typ, V
BACKUP
= 0V, register 09h = A5h.
Measured at V
CC
= typ, V
BACKUP
= 0V, register 09h = A6h.
Measured at V
CC
= typ, V
BACKUP
= 0V, register 09h = A7h.
SCL only.
SDA and SQW and
INT
.
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