参数资料
型号: DS1386
厂商: Maxim Integrated Products, Inc.
英文描述: Nonvolatile Static RAM with a Full Function Real Time Clock (RTC),(带完整功能的实时时钟静态RAM)
中文描述: RAMified看门狗计时器
文件页数: 2/16页
文件大小: 183K
代理商: DS1386
DS1386/DS1386P
070298 2/16
PIN DESCRIPTION
INTA
INTB(INTB)
A0–A14
DQ0–DQ7
CE
OE
– Interrupt Output A (open drain)
– Interrupt Output B (open drain)
– Address Inputs
– Data Input/Output
– Chip Enable
– Output Enable
WE
V
CC
GND
SQW
NC
X1, X2
V
BAT
– Write Enable
– +5 Volts
– Ground
– Square Wave Output
– No Connection
– Crystal Connection
– Battery Connection
DESCRIPTION
The DS1386 is a nonvolatile static RAM with a full func-
tion Real Time Clock (RTC), alarm, watchdog timer, and
interval timer which are all accessible in a Byte–wide
format. The DS1386 contains a lithium energy source
and a quartz crystal which eliminates the need for any
external circuitry. Data contained within 8K or 32K by
8–bit memory and the timekeeping registers can be
read or written in the same manner as bytewide static
RAM. The timekeeping registers are located in the first
14 bytes of memory space. Data is maintained in the
RAMified Timekeeper by intelligent control circuitry
which detects the status of V
CC
and write protects
memory when V
CC
is out of tolerance. The lithium ener-
gy source can maintain data and real time for over ten
years in the absence of V
CC
. Timekeeper information
includes hundredths of seconds, seconds, minutes,
hours, day, date, month, and year. The date at the end
of the month is automatically adjusted for months with
less than 31 days, including correction for leap year.
The RAMified Timekeeper operates in either 24 hour or
12 hour format with an AM/PM indicator. The watchdog
timer provides alarm interrupts and interval timing be-
tween 0.01 seconds and 99.99 seconds. The real time
alarm provides for preset times of up to one week. Inter-
rupts for both watchdog and RTC will operate when sys-
tem is powered down. Either can provide system
“wake-up” signals.
PACKAGES
The DS1386 is available in two packages (32–pin DIP
module and 34–pin PowerCap module). The 32–pin
Dip style module integrated the crystal, lithium energy
source, and silicon all in one package. The 34–pin Pow-
erCap Module Board is designed with contacts for con-
nection to a separate PowerCap (DS9034PCX) that
contains the crystal and battery. This design allows the
PowerCap to be mounted on top of the DS1386P after
the completion of the surface mount process. Mounting
the PowerCap after the surface mount process pre-
vents damage to the crystal and battery due to high tem-
peratures required for solder reflow. The PowerCap is
keyed to prevent reverse insertion. The PowerCap
Module Board and PowerCap are ordered separately
and shipped in separate containers. The part number
for the PowerCap is DS9034PCX.
OPERATION – READ REGISTERS
The DS1386 executes a read cycle whenever WE
(Write Enable) is inactive (High), CE (Chip Enable) and
OE (Output Enable) are active (Low). The unique ad-
dress specified by the address inputs (A0–A14) defines
which of the registers is to be accessed. Valid data will
be available to the eight data output drivers within t
ACC
(Access Time) after the last address input signal is
stable, providing that CE and OE access times are also
satisfied. If OE and CE access times are not satisfied,
then data access must be measured from the latter oc-
curring signal (CE or OE) and the limiting parameter is
either t
CO
for CE or t
OE
for OE rather than address ac-
cess.
OPERATION – WRITE REGISTERS
The DS1386 is in the write mode whenever the WE
(Write Enable) and CE (Chip Enable) signals are in the
active (Low) state after the address inputs are stable.
The latter occurring falling edge of CE or WE will deter-
mine the start of the write cycle. The write cycle is termi-
nated by the earlier rising edge of CE or WE. All address
inputs must be kept valid throughout the write cycle.
WE must return to the high state for a minimum recovery
state (t
WR
) before another cycle can be initiated. Data
must be valid on the data bus with sufficient Data
Set–Up (t
DS
) and Data Hold Time (t
DH
) with respect to
the earlier rising edge of CE or WE. The OE control sig-
nal should be kept inactive (High) during write cycles to
avoid bus contention. However, if the output bus has
been enabled (CE and OE active), then WE will disable
the outputs in t
ODW
from its falling edge.
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