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参数资料
| 型号： | DS1386P |
| 厂商： | Maxim Integrated Products, Inc. |
| 英文描述： | RAMified Watchdog Timekeeper(带完整功能的实时时钟静态RAM) |
| 中文描述： | RAMified看门狗计时器 |
| 文件页数： | 7/16页 |
| 文件大小： | 183K |
| 代理商： | DS1386P |
DS1386/DS1386P
070298 7/16
TIME OF DAY ALARM MASK BITS
Figure 3
(3)MINUTES
(5)HOURS
(7)DAYS
1
0
ALARM ONCE PER MINUTE
ALARM WHEN MINUTES MATCH
ALARM WHEN HOURS AND MINUTES MATCH
ALARM WHEN HOURS, MINUTES,
AND DAYS MATCH
1
1
1
1
1
0
0
0
0
0
NOTE: ANY OTHER BIT COMBINATIONS OF MASK BIT SETTINGS PRODUCE ILLOGICAL OPERATION.
REGISTER
COMMAND REGISTER
Address location 0Bh is the Command Register where
mask bits, control bits and flag bits reside. The opera-
tion of each bit is as follows:
TE –
Bit 7 Transfer enable – This bit when set to a logic 0
will disable the transfer of data between internal and ex-
ternal clock registers. The contents in the external clock
registers are now frozen and reads or writes will not be
affected with updates. This bit must be set to a logic 1 to
allow updates.
IPSW –
Bit 6 Interrupt switch – When set to a logic 1,
INTA is the Time of Day Alarm and INTB/(INTB) is the
Watchdog Alarm. When set to logic 0, this bit reverses
the output pins. INTA is now the Watchdog Alarm output
and INTB/(INTB) is the Time of Day Alarm output.
IBH/LO –
Bit 5 Interrupt B Sink or Source Current –
When this bit is set to a logic 1 and V
CC
is applied,
INTB/(INTB) will source current (see DC characteristics
IOH). When this bit is set to a logic 0, INTB will sink cur-
rent (see DC characteristics IOL).
PU/LVL –
Bit 4 Interrupt pulse mode or level mode –
This bit determines whether both interrupts will output a
pulse or level signal. When set to a logic 0, INTA and
INTB/(INTB) will be in the level mode. When this bit is
set to a logic 1, the pulse mode is selected and INTA will
sink current for a minimum of 3 ms and then release.
INTB/(INTB) will either sink or source current, depend-
ing on the condition of Bit 5, for a minimum of 3 ms and
then release. INTB will only source current when there
is a voltage present on V
CC
.
WAM –
Bit 3 Watchdog Alarm Mask – When this bit is set
to a logic 0, the Watchdog Interrupt output will be acti-
vated. The activated state is determined by bits 1,4,5,
and 6 of the COMMAND REGISTER. When this bit is
set to a logic 1, the Watchdog interrupt output is deacti-
vated.
TDM –
Bit 2 Time of Day Alarm Mask – When this bit is
set to a logic 0, the Time of Day Alarm Interrupt output
will be activated. The activated state is determined by
bits 0,4,5, and 6 of the COMMAND REGISTER. When
this bit is set to a logic 1 , the Time of Day Alarm interrupt
output is deactivated.
WAF –
Bit 1 Watchdog Alarm Flag – This bit is set to a
logic 1 when a watchdog alarm interrupt occurs. This bit
is read only.
The bit is reset when any of the Watchdog Alarm regis-
ters are accessed.
When the interrupt is in the pulse mode (see bit 4 defini-
tion), this flag will be in the logic 1 state only during the
time the interrupt is active.
TDF –
Bit 0 Time of Day Flag – This is a read only bit.
This bit is set to a logic 1 when a Time of Day alarm has
occurred. The time the alarm occurred can be deter-
mined by reading the Time of Day Alarm registers. This
bit is reset to a logic 0 state when any of the Time of Day
Alarm registers are accessed.
When the interrupt is in the pulse mode (see bit 4 defini-
tion), this flag will be in the logic 1 state only during the
time the interrupt is active.
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| DS1386P08-120 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:RAMified Watchdog Timekeeper |
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| DS1386P-32-120+ | 功能描述:实时时钟 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
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