参数资料
型号: DS1390U-18
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: XO, clock
英文描述: RIBBON CABLE, 40WAY, PER M; Cores, No. of:40; Conductor make-up:7/36AWG; Wire size, AWG:28AWG; Impedance:119R; Pitch:1.27mm; Voltage rating, AC:50V; Colour:Grey; Capacitance:70.5pF/m; Approval Bodies:UL; Approval category:Style RoHS Compliant: Yes
中文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO10
封装: MO-187CBA, MICRO, SOP-10
文件页数: 16/24页
文件大小: 742K
代理商: DS1390U-18
D
Bit 7: Enable Oscillator (
EOSC
).
When set to logic 0,
this bit starts the oscillator. When this bit is set to logic
1, the oscillator is stopped whenever the device is pow-
ered by V
BACKUP
. The oscillator is always enabled
when V
CC
is valid. This bit is enabled (logic 0) when
V
CC
is first applied.
Bit 5: Battery-Backed Square-Wave and Interrupt
Enable (BBSQI).
This bit when set to logic 1 enables
the square wave or interrupt output when V
CC
is absent
and the DS1390/DS1392/DS1393 are being powered
by the V
BACKUP
pin. When BBSQI is logic 0, the
SQW/
INT
pin (or SQW and
INT
pins) goes high imped-
ance when V
CC
falls below the power-fail trip point.
This bit is disabled (logic 0) when power is first applied.
Bits 4 and 3: Rate Select (RS2 and RS1).
These bits
control the frequency of the square-wave output when
the square wave has been enabled. The table below
shows the square-wave frequencies that can be select-
ed with the RS bits. These bits are both set to logic 1
(32kHz) when power is first applied.
Bit 2: Interrupt Control (INTCN).
This bit controls the
SQW/
INT
signal. When the INTCN bit is set to logic 0, a
square wave is output on the SQW/
INT
pin. The oscilla-
tor must also be enabled for the square wave to be out-
put. When the INTCN bit is set to logic 1, a match
between the timekeeping registers and either of the
alarm registers then activates the SQW/
INT
(provided
the alarm is also enabled). The corresponding alarm
flag is always set, regardless of the state of the INTCN
bit. The INTCN bit is set to logic 0 when power is first
applied.
Bit 0: Alarm Interrupt Enable (AIE).
When set to logic
1, this bit permits the alarm flag (AF) bit in the status
register to assert SQW/
INT
(when INTCN = 1). When
the AIE bit is set to logic 0 or INTCN is set to logic 0,
the AF bit does not initiate the SQW/
INT
signal. The AIE
bit is disabled (logic 0) when power is first applied.
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
16
____________________________________________________________________
BIT 7
EOSC
BIT 6
0
BIT 5
BBSQI
BIT 4
RS2
BIT 3
RS1
BIT 2
INTCN
BIT 1
0
BIT 0
AIE
Control Register (0D/8Dh) (DS1390/DS1393 Only)
BIT 7
EOSC
BIT 6
0
BIT 5
X
BIT 4
X
BIT 3
X
BIT 2
X
BIT 1
0
BIT 0
X
Control Register (0D/8Dh) (DS1391 Only)
RS2
0
0
1
1
RS1
0
1
0
1
SQUARE-WAVE OUTPUT FREQUENCY
1Hz
4.096kHz
8.192kHz
32.768kHz
Special-Purpose Registers
The DS1390–DS1393 have three additional registers
(control, status, and trickle charger) that control the
RTC, alarms, square-wave output, and trickle charger.
Control bits used in the DS1390 become general-pur-
pose, battery-backed, nonvolatile SRAM bits in the
DS1391.
相关PDF资料
PDF描述
DS1390 Low-Voltage SPI/3-Wire RTCs with Trickle Charger
DS1392U-33 Low-Voltage SPI/3-Wire RTCs with Trickle Charger
DS1391U-3 IGBT Module; Continuous Collector Current, Ic:200A; Collector Emitter Saturation Voltage, Vce(sat):3.4V; Power Dissipation, Pd:1500W; Collector Current:200A; Collector Emitter Voltage, Vceo:1.2kV; Leaded Process Compatible:No RoHS Compliant: No
DS1391U-33 Low-Voltage SPI/3-Wire RTCs with Trickle Charger
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DS1390U-18+ 功能描述:实时时钟 Low-V SPI/3-Wire With Trickle Charger RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube
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DS1390U-3+T&R 功能描述:实时时钟 Low-V SPI/3-Wire With Trickle Charger RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube