参数资料
型号: DS1410E
厂商: DALLAS SEMICONDUCTOR
元件分类: 微控制器/微处理器
英文描述: Parallel Port Adapter(并行端口适配器)
中文描述: SPECIALTY MICROPROCESSOR CIRCUIT
文件页数: 2/7页
文件大小: 43K
代理商: DS1410E
DS1410E
021798 2/7
OPERATION
The DS1410E utilizes a DS1481 1–Wire
TM
Bus Master
to communicate with iButtons. The DS1481 generates
either a read/write bit “time slot” or a reset on the I/O pin
(1–Wire bus). The operation performed is determined
by the states of input pins 2 and 3 on the port adapter as
follows:
TIME SLOT
PIN 2
PIN 3
Read 0, Read1,
Write 1
logic high
logic high (see
Figure 1)
Write 0
logic low
logic high (see
Figure 2)
1–Wire Reset
logic high
logic low (see
Figure 3)
After input pins 2 and 3 have been set, the time slot
begins by driving input pin 14 to its active state (low). A
falling edge on input pin 14 causes the DS1481 to drive
input pins 11 and 13 low (indicating a time slot is in
progress).
While input pins 11 and 13 are low, the host processor is
free to perform other tasks (including running the print
spooler). When the time slot is complete input pins 11
and 13 are restored to the states of output pins 11
and 13.
When the host detects that one or both of the busy sig-
nals has returned high, it must query the result of the
time slot. This is accomplished by driving input pin 2
low. If the 1–Wire bus was low (read 0, write 0, or pres-
ence detect) the DS1481 drives both input pins 11 and
13 low (this state was held until input pins 14 or 2 return
high). Otherwise it propagates the states of output pins
11 and 13.
After the host reads the time slot result it must drive input
pin 14 to its inactive state (high). The DS1481 will then
set input pins 11 and 13 to the state of output pins 11
and 13.
DS1410E 1–WIRE TIMING GENERATION
For all time slots, the DS1481 samples the I/O pin at t
SIO
(see Figure 3). The DS1481 waits a minimum of 60
μ
s
from the start of the time slot and de–asserts input pins
11 and 13.
When a reset is requested, the DS1481 drives the I/O
pin low for at least 480
μ
s and then releases it. During a
normal reset the I/O pin immediately begins to return
high.
If a 1–Wire device is present on the I/O line it pulls I/O
low after time T (15
μ
s < T < 60
μ
s) from the previous
rising edge. The 1–Wire device(s) holds the I/O line low
for 4T and then releases it, allowing the I/O line to return
high. This is the presence detect pulse. The I/O line
must remain high (in its idle state) for at least 3T before
the 1–Wire device(s) is ready for further communica-
tion. To insure this idle high time is satisfied, the DS1481
does not release input pins 11 and 13 for at least 960
μ
s
(measured from the 1st falling edge on the I/O pin).
If after 480
μ
s of low time the I/O line did not return high,
either the I/O line has been shorted to ground or there is
at least one 1–Wire device connected to the I/O line
which is issuing an alarm interrupt (see Figure 3). In this
case the DS1481 waits for I/O to return high for an addi-
tional 3840
μ
s (64 * 60). If time expires the I/O line is
assumed to be shorted and the DS1481 releases input
pins 11 and 13. If the I/O line returns high, the DS1481
continues to monitor the presence detect portion of the
reset (as described above) as for the non–interrupt
case. Note that the 3T idle high time is still required after
the presence detect ends.
OVERDRIVE
The DS1481 also supports overdrive communication
with overdrive capable 1–Wire devices. When the
DS1481 powers up it is in normal mode (i.e., OD = 0,
Figure 1). To toggle to overdrive mode the host sets
input pins 2 and 3 low and drives Input pin 14 low. The
DS1481 toggles the OD (OverDrive) bit to a logic high
and returns the states of output pins 11 and 13 on input
pins 11 and 13. Overdrive mode is cleared in the same
way. When overdrive is turned off (OD = 0). Input pins 11
and 13 are driven low to report the state of the OD bit.
When OD = 1, communication with the 1–Wire devices
is exactly as described in the operation section above.
The actual 1–Wire timing for both modes of operation is
described in figures 1, 2 and 3 below.
Note that when toggling the OD bit there is no change on
the I/O line.
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