参数资料
型号: DS1486P-120+
厂商: Maxim Integrated Products
文件页数: 9/14页
文件大小: 0K
描述: IC TIMEKEEPER RAM 1MB 34-PCM
标准包装: 40
类型: 时钟/日历
特点: 警报器,闰年,NVSRAM,方波输出,监视计时器
存储容量: 128KB
时间格式: HH:MM:SS:hh(12/24 小时)
数据格式: YY-MM-DD-dd
接口: 并联
电源电压: 4.5 V ~ 5.5 V
电压 - 电源,电池: 3.3V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 34-PowerCap? 模块
供应商设备封装: 34-PowerCap 模块
包装: 管件
DS1486/DS1486P
4 of 14
OPERATION—WRITE REGISTERS
The DS1486 is in the write mode whenever the
WE (Write Enable) and CE (Chip Enable) signals are in
the active (Low) state after the address inputs are stable. The latter occurring falling edge of
CE or WE
will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of
CE
or
WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state
for a minimum recovery state (tWR) before another cycle can be initiated. Data must be valid on the data
bus with sufficient Data Set-Up (tDS) and Data Hold Time (tDH) with respect to the earlier rising edge of
CE or WE. The OE control signal should be kept inactive (High) during write cycles to avoid bus
contention. However, if the output bus has been enabled (
CE and OE active), then WE will disable the
outputs in tODW from its falling edge.
DATA RETENTION
The RAMified Timekeeper provides full functional capability when VCC is greater than 4.5V. When VCC
falls below the power fail trip-point (VTP), the internal CE signal is forced high, blocking access (Write-
Protect). While in the data retention mode, all inputs are “don’t cares,” SQW and DQ0–DQ7 go to a high-
impedance state. The two interrupts
INTA and INTB (INTB) and the internal clock and timers continue
to run regardless of the level of VCC. However, it is important to insure that the pull-up resistors used with
the interrupt pins are never pulled up to a value that is greater than VCC + 0.3V. As VCC falls below
approximately 3.0V, a power switching circuit turns the internal lithium energy source on to maintain the
clock and timer data functionality. It is also required to ensure that during this time (battery-backup
mode), that the voltage present at
INTA and INTB (INTB) never exceeds VBAT. During power-up, when
VCC rises above VBAT, the power-switching circuit connects external VCC and disconnects the internal
lithium energy source. Normal operation can resume after VCC exceeds 4.5V for a period of 200ms.
RAMIFIED TIMEKEEPER REGISTERS
The RAMified timekeeper has 14 registers that are 8 bits wide that contain all the timekeeping, alarm,
watchdog, and control information. The clock, calendar, alarm, and watchdog registers are memory
locations that contain external (user-accessible) and internal copies of the data. The external copies are
independent of internal functions, except that they are updated periodically by the simultaneous transfer
of the incremented internal copy (see Figure 1). The Command Register bits are affected by both internal
and external functions. This register will be discussed later. Registers 0, 1, 2, 4, 6, 8, 9, and A contain
time-of-day and date information (see Figure 2). Time-of-day information is stored in BCD. Registers 3,
5, and 7 contain the Time-of-Day Alarm information. Time-of-Day Alarm information is stored in BCD.
Register B is the Command Register and information in this register is binary. Registers C and D are the
Watchdog Alarm Registers and information that is stored in these two registers is in BCD. Registers E
through 1FFFF are user bytes and can be used to maintain data at the user’s discretion.
CLOCK ACCURACY (DIP MODULE)
The DS1486 is guaranteed to keep time accuracy to within
±1 minute per month at +25°C.
CLOCK ACCURACY (PowerCap MODULE)
The DS1486P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within ±1.53 minutes per month (35ppm) at +25°C.
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