
DS1500/DS1510
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USING THE CLOCK ALARM
The alarm settings and control for the DS1500/DS1510 reside within registers 08h - 0Bh (see Table 3).
The TIE bit and alarm mask bits AM1-AM4 must be set as described below for the IRQ or PWR outputs
to be activated for a matched alarm condition.
The alarm can be programmed to activate on a specific day of the month, day of the week, or repeat every
day, hour, minute, or second. It can also be programmed to go off while the DS1500/DS1510 is in the
battery-backed state of operation to serve as a system wake-up. Alarm mask bits AM1-AM4 control the
alarm mode. Table 2 shows the possible settings. Configurations not listed in the table default to the
once per second mode to notify the user of an incorrect alarm setting. When the RTC register values
match alarm register settings, the Time of Day/Date alarm Flag TDF bit is set to a "1". Once the TDF flag
is set, the TIE bit enables the alarm to activate the IRQ pin. The TPE bit enables the alarm flag to activate
the PWR pin.
ALARM MASK BITS Table 2
DY/DT
AM3
AM2
AM1
ALARM RATE
X
1
Once per Second
X
1
0
When seconds match
X
1
0
When minutes and seconds match
X
0
When hours, minutes, and seconds match
0
When date, hours, minutes, and seconds match
1
0
When day, hours, minutes, and seconds match
USING THE WATCHDOG TIMER
The watchdog timer can be used to restart an out-of-control processor. The watchdog timer is user
programmable in 10 milli-second intervals ranging from 0.01 seconds to 99.99 seconds.
The user
programs the watchdog timer by setting the desired amount of time-out into the two BCD Watchdog
Registers (Address 0 Ch and 0Dh). For example: writing 60h in the watchdog register 0 Ch and 00h to
watchdog register 0 Dh will set the watchdog time-out to 600 milli-seconds. If the processor does not
access the timer with a write within the specified period, both the Watchdog Flag WDF and the Interrupt
Request Flag IRQF will be set. If the Watchdog Enable bit WDE is enabled, then either IRQ or RST will
go active depending on the state of the Watchdog Steering Bit WDS. The watchdog will be reloaded and
restarted whenever the watchdog times out. The WDF bit will be set to a "1" regardless of the state of
WDE to serve as an indication to the processor that a watchdog time out has occurred.
The watchdog timer is reloaded when the processor performs a write of the Watchdog registers. The
time-out period then starts over. The watchdog timer is disabled by writing a value of 00h to both
watchdog registers. The watchdog function is automatically disabled upon power-up.
The following summarizes the configurations in which the watchdog can be used.
1. WDE=0 and WDS=0: WDF will be set.
2. WDE=0 and WDS=1: WDF will be set.
3. WDE=1 and WDS=0: WDF and IRQF will be set, and the IRQ pin will be pulled low.
4. WDE=1 and WDS=1: WDF will be set, the RST pin will be pulled low for a duration of 40 ms to
200 ms, and ‘WDE’ will be reset to ‘0’.