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参数资料
| 型号： | DS1553P-100 |
| 厂商： | DALLAS SEMICONDUCTOR |
| 元件分类： | Timer or RTC |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, DMA34 |
| 封装： | POWERCAP MODULE-34 |
| 文件页数： | 13/19页 |
| 文件大小： | 278K |
| 代理商： | DS1553P-100 |
DS1553
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DS1553 BLOCK DIAGRAM Figure 1
DS1553 OPERATING MODES Table 1
VCC
CE
OE
WE
DQ0-DQ7
MODE
POWER
VIH
X
HIGH-Z
DESELECT
STANDBY
VIL
XVIL
DIN
WRITE
ACTIVE
VIL
VIH
DOUT
READ
ACTIVE
VCC > VPF
VIL
VIH
HIGH-Z
READ
ACTIVE
VSO < VCC <VPF
X
HIGH-Z
DESELECT
CMOS STANDBY
<VBAT
X
HIGH-Z
DATA
RETENTION
BATTERY
CURRENT
DATA READ MODE
The DS1553 is in the read mode whenever CE (chip enable) is low and WE (write enable) is high. The
device architecture allows ripple-through access to any valid address location. Valid data will be available
at the DQ pins within tAA after the last address input is stable, providing that CE and OE access times are
satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip enable
access (tCEA) or at output enable access time (tOEA). The state of the data input/output pins (DQ) is
controlled by CE and OE . If the outputs are activated before tAA, the data lines are driven to an
intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data
will remain valid for output data hold time (tOH) but will then go indeterminate until the next address
access.
DATA WRITE MODE
The DS1553 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout
the cycle. CE and WE must return inactive for a minimum of tWR prior to the initiation of a subsequent
read or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for tDH
afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be
active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs tWEZ after WE goes active.
相关PDF资料 |
PDF描述 |
|---|---|
| DS1554-70 | 0 TIMER(S), REAL TIME CLOCK, PDMA32 |
| DS1554WP-120 | 0 TIMER(S), REAL TIME CLOCK |
| DS1554W-120 | 0 TIMER(S), REAL TIME CLOCK, PDMA32 |
| DS1554P-70 | 0 TIMER(S), REAL TIME CLOCK, DMA34 |
| DS1554 | REAL TIME CLOCK, DMA32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1553P-100+ | 功能描述:实时时钟 64kB NV RAM Timekeeper RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| DS1553P-70 | 功能描述:实时时钟 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| DS1553P-70+ | 功能描述:实时时钟 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| DS1553P-85+ | 功能描述:实时时钟 64kB NV RAM Timekeeper RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| DS1553W-120 | 功能描述:实时时钟 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
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