参数资料
型号: DS1554P-70IND+
厂商: Maxim Integrated Products
文件页数: 14/18页
文件大小: 0K
描述: IC RTC RAM Y2K 5V 70NS 34-PCM
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 40
类型: 时钟/日历
特点: 警报器,闰年,NVSRAM,监视计时器,Y2K
存储容量: 32KB
时间格式: HH:MM:SS(24 小时)
数据格式: YY-MM-DD-dd
接口: 并联
电源电压: 4.5 V ~ 5.5 V
电压 - 电源,电池: 3V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 34-PowerCap? 模块
供应商设备封装: 34-PowerCap 模块
包装: 管件
DS1554 256k, Nonvolatile, Y2K-Compliant Timekeeping RAM
5 of 18
DATA-READ MODE
The DS1554 is in the read mode whenever
CE (chip enable) is low and WE (write enable) is high. The
device architecture allows ripple-through access to any valid address location. Valid data will be available
at the DQ pins within tAA after the last address input is stable, providing that CE and OE access times are
satisfied. If
CE or OE access times are not met, valid data will be available at the latter of chip enable
access (tCEA) or at output enable access time (tOEA). The state of the data input/output pins (DQ) is
controlled by
CE and OE. If the outputs are activated before t
AA, the data lines are driven to an
intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data
will remain valid for output data hold time (tOH ) but will then go indeterminate until the next address
access.
DATA-WRITE MODE
The DS1554 is in the write mode whenever
WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of
WE or CE. The addresses must be held valid throughout the
cycle.
CE and WE must return inactive for a minimum of t
WR prior to the initiation of a subsequent read
or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for tDH afterward. In
a typical application, the
OE signal will be high during a write cycle. However, OE can be active
provided that care is taken with the data bus to avoid bus contention. If
OE is low prior to WE
transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on
WE will then disable the outputs t
WEZ after WE goes active.
DATA-RETENTION MODE
The 5V device is fully accessible and data can be written and read only when VCC is greater than VPF.
However, when VCC is below the power-fail point VPF (point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch
point VSO (battery supply level), device power is switched from the VCC pin to the internal backup lithium
battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal
levels.
The 3.3V device is fully accessible and data can be written and read only when VCC is greater than VPF.
When VCC falls below VPF, access to the device is inhibited. If VPF is less than VSO, the device power is
switched from VCC to the internal backup lithium battery when VCC drops below VPF. If VPF is greater
than VSO, the device power is switched from VCC to the internal backup lithium battery when VCC drops
below VSO. RTC operation and SRAM data are maintained from the battery until VCC is returned to
nominal levels.
All control, data, and address signals must be powered down when VCC is powered down.
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