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参数资料
| 型号： | DS1558Y-TRL |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 14/18页 |
| 文件大小： | 0K |
| 描述： | IC RTC W/NV RAM 5V 48-TQFP |
| 标准包装： | 2,000 |
| 类型： | 时钟/日历 |
| 特点： | 警报器，闰年，监视计时器，Y2K |
| 时间格式： | HH:MM:SS（24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电压 - 电源，电池： | 2.5 V ~ 3.7 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
DS1558
5 of 18
Figure 1. BLOCK DIAGRAM
ES
VCC
Table 1. OPERATING MOD
CE
OE
WE
DQ0–DQ7
MODE
POWER
VIH
X
High-Z
Deselect
Standby
VIL
X
VIL
DIN
Write
Active
VIL
VIH
DOUT
Read
Active
VCC > VPF
VIL
VIH
High-Z
Read
Active
VSO < VCC < VPF
X
High-Z
Deselect
CMOS Standby
VCC < VSO < VPF
X
High-Z
Data Retention
Battery Current
DATA READ MODE
The DS1558 is in the read mode whenever CE is low and WE is high. The device architecture allows
gh access to any valid address location. Valid data is available at the DQ pins within tAA after
the last address input is stable, provided that
ripple-throu
CE
and OE access times are satisfied. If CE or OE access
et, valid data is available at the latter of chip-enable access (tCEA) or at output-enable
(tOEA). The state of the data input/output pins (DQ) is controlled by
times are not m
access time
CE
and OE . If the
ated before tAA, the data lines are driven to an intermediate state until tAA. If the address
inputs are changed while
outputs are activ
CE
and OE remain valid, output data remains valid for output-data hold time
), but then goes indeterminate until the next address access.
(tOH
NOTE: ANY U
S THE RTC.
NUSED UPPER ADDRESS PINS MUST BE CONNECTED TO VCC TO PROPERLY ADDRES
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相关代理商/技术参数 |
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|---|---|
| DS-1561 | 制造商:M/A-COM Technology Solutions 功能描述:POWER_DIVIDER - Bulk |
| DS1585S | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| DS1587L | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| DS1589 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| DS1589S | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
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