参数资料
型号: DS1644P-120
厂商: Maxim Integrated Products
文件页数: 8/14页
文件大小: 0K
描述: IC RAM TIMEKEEP NV 120NS 34-PCM
标准包装: 40
类型: 时钟/日历
特点: 闰年,NVSRAM
存储容量: 32KB
时间格式: HH:MM:SS(24 小时)
数据格式: YY-MM-DD-dd
接口: 并联
电源电压: 4.5 V ~ 5.5 V
电压 - 电源,电池: 3V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 34-PowerCap? 模块
供应商设备封装: 34-PowerCap 模块
包装: 管件
其它名称: DS1644P120
DS1644/DS1644P
3 of 14
PACKAGES
The DS1644 is available in two packages (28-pin DIP and 34-pin PowerCap module). The 28-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1644P after the completion of the surface-mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
CLOCK OPERATIONS—READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1644 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register.
As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is day, date, and time that was present at the moment the halt command was issued. However,
the internal clock registers of the double-buffered system continue to update so that the clock accuracy is
not affected by the access of data. All of the DS1644 registers are updated simultaneously after the clock
status is reset. Updating is within a second after the read bit is written to 0.
DS1644 BLOCK DIAGRAM Figure 1
DS1644 TRUTH TABLE Table 1
VCC
CE
OE
WE
MODE
DQ
POWER
VIH
X
DESELECT
HIGH-Z
STANDBY
X
DESELECT
HIGH-Z
STANDBY
VIL
X
VIL
WRITE
DATA IN
ACTIVE
VIL
VIH
READ
DATA OUT
ACTIVE
5V
10%
VIL
VIH
READ
HIGH-Z
ACTIVE
<4.5V >VBAT
X
DESELECT
HIGH-Z
CMOS STANDBY
<VBAT
X
DESELECT
HIGH-Z
DATA RETENTION
MODE
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