参数资料
型号: DS1646P-120
厂商: DALLAS SEMICONDUCTOR
元件分类: Timer or RTC
英文描述: 0 TIMER(S), REAL TIME CLOCK, DMA34
封装: POWERCAP MODULE BOARD-34
文件页数: 6/11页
文件大小: 382K
代理商: DS1646P-120
4 of 11
080299
CLOCK ACCURACY (DIP MODULE)
The DS1646 is guaranteed to keep time accuracy to within
±1 minute per month at 25°C.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1646P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within
±1.53 minutes per month (35 PPM) at 25°C.
DS1646 REGISTER MAP - BANK1 Table 2
DATA
ADDRESS
B7
B6
B5
B4
B3
B2
B1
B0
FUNCTION
1FFF
-
YEAR
00-99
1FFE
X
-
MONTH
01-12
1FFD
X
-
DATE
01-31
1FFC
X
FT
X
-
DAY
01-07
1FFB
X
-
HOUR
00-23
1FFA
X
-
MINUTES
00-59
1FF9
OSC
-
SECONDS
00-59
1FF8
W
R
X
CONTROL
A
OSC
= STOP BIT
R = READ BIT
FT = FREQUENCY TEST
W
= WRITE BIT
X = UNUSED
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1646 is in the read mode whenever WE (write enable) is high; CE (chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NVSRAM. Valid
data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip-enable access (tCEA) or at output enable access time (tOEA). The state of the
data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before tAA, the data
lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1646 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring high to low transition of WE and CE . The addresses must be held valid
throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of
another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH
afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be
active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs tWEZ after WE goes active.
相关PDF资料
PDF描述
DS1646L-120 0 TIMER(S), REAL TIME CLOCK, DSO34
DS1646 0 TIMER(S), REAL TIME CLOCK, DMA32
DS1646P 0 TIMER(S), REAL TIME CLOCK, DMA34
DS1647-120 0 TIMER(S), REAL TIME CLOCK, DMA28
DS1647P-120 0 TIMER(S), REAL TIME CLOCK, DMA34
相关代理商/技术参数
参数描述
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