参数资料
型号: DS1672S-33+
厂商: Maxim Integrated Products
文件页数: 11/15页
文件大小: 0K
描述: IC TIMEKEEPER 3.3V 32-BIT 8-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 100
类型: 二进制计数器
特点: 涓流充电器
时间格式: 二进制
数据格式: 二进制
接口: I²C,2 线串口
电源电压: 2.97 V ~ 3.63 V
电压 - 电源,电池: 1.3 V ~ 3.63 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
产品目录页面: 1436 (CN2011-ZH PDF)
DS1672
5 of 15
AC ELECTRICAL CHARACTERISTICS
(VCC = 0V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock
Frequency
fSCL
Fast mode
100
400
kHz
Standard mode
100
Bus Free Time
Between a STOP and
START Condition
tBUF
Fast mode
1.3
s
Standard mode
4.7
Hold Time
(Repeated) START
Condition (Note 6)
tHD:STA
Fast mode
0.6
s
Standard mode
4.0
LOW Period of SCL
Clock
tLOW
Fast mode
1.3
s
Standard mode
4.7
HIGH Period of SCL
Clock
tHIGH
Fast mode
0.6
s
Standard mode
4.0
Setup Time for a
Repeated START
Condition
tSU:STA
Fast mode
0.6
s
Standard mode
4.7
Data Hold Time
(Notes 7, 8)
tHD:DAT
Fast mode
0
0.9
s
Standard mode
0
Data Setup Time
(Note 9)
tSU:DAT
Fast mode
100
ns
Standard mode
250
Rise Time of Both
SDA and SCL
Signals (Note 10)
tR
Fast mode
20 + 0.1CB
300
ns
Standard mode
1000
Fall Time of Both
SDA and SCL
Signals (Note 10)
tF
Fast mode
20 + 0.1CB
300
ns
Standard mode
300
Setup Time for STOP
Condition
tSU:STO
Fast mode
0.6
s
Standard mode
4.0
Capacitive Load for
Each Bus Line
(Note 10)
CB
400
pF
I/O Capacitance
CI/O
10
pF
Note 6: After this period, the first clock pulse is generated.
Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referenced to the VIHMIN of the SCL signal) in
order to bridge the undefined region of the falling edge of SCL.
Note 8:The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 9: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT
≥ to 250ns must then be met. This will
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250ns before the SCL
line is released.
Note 10: CB–Total capacitance of one bus line in pF.
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