参数资料
型号: DS1743WP-150
厂商: DALLAS SEMICONDUCTOR
元件分类: Timer or RTC
英文描述: 0 TIMER(S), REAL TIME CLOCK, DMA34
封装: 0.700 INCH, MODULE, POWERCAP-34
文件页数: 11/17页
文件大小: 247K
代理商: DS1743WP-150
DS1743/DS1743P
3 of 17
DS1743 BLOCK DIAGRAM Figure 1
DS1743 TRUTH TABLE Table 1
VCC
CE
CE2
OE
WE
MODE
DQ
POWER
VIH
X
DESELECT
HIGH-Z
STANDBY
XVIL
X
DESELECT
HIGH-Z
STANDBY
VIL
VIH
XVIL
WRITE
DATA IN
ACTIVE
VIL
VIH
VIL
VIH
READ
DATA OUT
ACTIVE
VCC>VPF
VIL
VIH
READ
HIGH-Z
ACTIVE
VSO<VCC<VPF
X
DESELECT
HIGH-Z
CMOS STANDBY
VCC<VSO<VPF
X
DESELECT
HIGH-Z
DATA RETENTION
MODE
SETTING THE CLOCK
As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like the read
bit, halts updates to the DS1743 registers. The user can then load them with the correct day, date and time
data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock
counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers, see
Table 2. Setting it to a 1 stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for
access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and
stable).
相关PDF资料
PDF描述
DS1743W-150 0 TIMER(S), REAL TIME CLOCK, DMA28
DS1743P-100 0 TIMER(S), REAL TIME CLOCK, DMA34
DS1744-70 REAL TIME CLOCK, PDMA28
DS1744WP-120 REAL TIME CLOCK, DMA34
DS1744P-70 0 TIMER(S), REAL TIME CLOCK, DMA28
相关代理商/技术参数
参数描述
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