参数资料
型号: DS1746-70IND
厂商: Maxim Integrated Products
文件页数: 13/16页
文件大小: 0K
描述: IC RTC RAM Y2K 5V 70NS 32-EDIP
标准包装: 11
类型: 时钟/日历
特点: 闰年,NVSRAM,Y2K
存储容量: 128KB
时间格式: HH:MM:SS(24 小时)
数据格式: YY-MM-DD-dd
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 32-DIP 模块(0.600",15.24mm)
供应商设备封装: 32-EDIP
包装: 管件
DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs
6 of 16
CLOCK ACCURACY (PowerCap MODULE)
The DS1746 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C. The
electrical environment also affects clock accuracy and caution should be taken to place the RTC in the
lowest-level EMI section of the PC board layout. For additional information, refer to Application Note
58.
Table 2. Register Map
ADDRESS
DATA
FUNCTION RANGE
B7
B6
B5
B4
B3
B2
B1
B0
1FFFF
10 Year
Year
00-99
1FFFE
X
10 Month
Month
01-12
1FFFD
X
10 Date
Date
01-31
1FFFC
BF
FT
X
Day
01-07
1FFFB
X
10 Hour
Hour
00-23
1FFFA
X
10 Minutes
Minutes
00-59
1FFF9
OSC
10 Seconds
Seconds
00-59
1FFF8
W
R
10 Century
Century
00-39
OSC
= Stop Bit
R = Read Bit
FT = Frequency Test
W = Write Bit
X = See Note
BF = Battery Flag
Note: All indicated “X” bits are not used but must be set to “0” during a write cycle to ensure proper clock operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1746 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and
states are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable
access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE and OE. If the outputs
are activated before tAA, the data lines are driven to an intermediate state until tAA . If the address inputs
are changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH)
but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1746 is in the write mode whenever WE, and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE, or CE. The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDS afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the
data bus can become active with read data defined by the address inputs. A low transition on WE will
then disable the output tWEZ after WE goes active.
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