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| 型号： | DS1780E/T&R |
| 厂商： | Maxim Integrated |
| 文件页数： | 18/28页 |
| 文件大小： | 0K |
| 描述： | IC CPU PERIPHERAL MON 24-TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1,000 |
| 功能： | 温度监控器，CPU 外围设备 |
| 传感器类型： | 内部 |
| 感应温度： | -40°C ~ 125°C |
| 精确度： | ±12°C（最小值） |
| 拓扑： | ADC（三角积分型），比较器，风扇速度控制，寄存器库 |
| 输出类型： | I²C?/SMBus? |
| 输出警报： | 无 |
| 输出风扇： | 是 |
| 电源电压： | 2.8 V ~ 5.75 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
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DS1780
INTERRUPT INT STATUS REGISTER 2 (ADDRESS 0X42; POWER-UP
DEFAULT=00h) Table 10.4
BIT
0
1
2
3
4
5
6
7
NAME
+12V_Error
-12V/
V CCP2 _Error
Reserved
Reserved
Chassis_Error
Reserved
Reserved
Reserved
R/W
R
R
R
R
R
R
R
R
DESCRIPTION
A 1 indicates a High or Low limit has been exceeded.
A 1 indicates a High or Low limit has been exceeded.
0
0
A 1 indicates Chassis Intrusion has gone high.
0
0
0
Note: Anytime the INT Status Registers are read out, the conditions (i.e., Registers) that are read are
automatically reset to power-up state (except CHS, which can only be cleared by CHS reset). In the case
of the VOLTAGE priority indication, if two or more voltages were out of LIMITS, then another
indication would automatically be generated if it were not handled during the ISR.
The errant voltage may be masked until the operator has time to clear the errant condition or set the limit
higher/lower.
INT MASK REGISTER 1 (ADDRESS 0X43; POWER-UP DEFAULT=00h)
Table 10.5
BIT
NAME
R/W
DESCRIPTION
0
1
2
3
4
5
6
7
+2.5V
+V CCP1
+3.3V
+5V
Temp
Reserved
FAN1
FAN2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
A 1 disables the corresponding interrupt status bit for INT
A 1 disables the corresponding interrupt status bit for INT
A 1 disables the corresponding interrupt status bit for INT
A 1 disables the corresponding interrupt status bit for INT
A 1 disables the corresponding interrupt status bit for INT
Power on default = 0.
A 1 disables the corresponding interrupt status bit for INT
A 1 disables the corresponding interrupt status bit for INT
interrupt.
interrupt.
interrupt.
interrupt.
interrupt.
interrupt.
interrupt.
INT MASK REGISTER 2 (ADDRESS 0X44; POWER-UP DEFAULT=00h)
Table 10.6
BIT
0
1
2
3
NAME
+12V
-12V/V CCP2
Reserved
Reserved
R/W
R/W
R/W
R/W
R/W
DESCRIPTION
A 1 disables the corresponding interrupt status bit for INT interrupt.
A 1 disables the corresponding interrupt status bit for INT interrupt.
Power-up Default = 0.
Power-up Default = 0.
CHS_sec
4
5
6
7
(Chassis
Intrusion)
Reserved
Reserved
Reset Enable
R/W
R/W
R/W
R/W
A 1 disables the corresponding interrupt status bit for
Power-up Default = 0.
Power-up Default = 0.
A 1 enables the RESET in the configuration register.
INT
interrupt.
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