参数资料
型号: DS1803Z-100
厂商: Maxim Integrated Products
文件页数: 10/11页
文件大小: 0K
描述: IC POT DUAL ADDRESS 100K 16-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
接片: 256
电阻(欧姆): 100k
电路数: 2
温度系数: 标准值 750 ppm/°C
存储器类型: 易失
接口: I²C(芯片选择)
电源电压: 2.7 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SOIC
包装: 管件
其它名称: DS1803Z100
DS1803
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5. After this period, the first clock pulse is generated.
6. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
VIHMIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL signal.
8. A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line tRMAX+ tSU:DAT = 1000 + 250=1250 ns before the SCL line is released.
9. CB - total capacitance of one bus line in picofarads, timing referenced to (0.9)(VCC) and (0.1)(VCC).
10. Typical values are for tA = 25°C and nominal supply voltage.
11. -3 dB cutoff frequency characteristics for the DS1803 depend on potentiometer total resistance:
DS1803-010; 1 MHz, DS1803-50; 200 kHz, DS1803-100; 100 kHz.
12. Address Inputs, A0, A1, and A2, should be tied to either VCC or GND depending on the desired
address selections.
13. Absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper
position. Device test limits are
±1.6 LSB.
14. Relative linearity is used to determine the change in voltage between successive tap positions. Device
test limits
±0.5 LSB.
15. Fast mode.
16. Standard mode.
17. Valid at 25
°C only.
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