参数资料
型号: DS1822-PAR+T&R
厂商: Maxim Integrated
文件页数: 2/19页
文件大小: 0K
描述: IC THERMOMETER ECONO DIG TO-92
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
感应温度: -55°C ~ 125°C
输出类型: 数字
电源电压: 3 V ~ 5 V
精确度: ±2°C
封装/外壳: TO-226-3、TO-92-3(TO-226AA)成形引线
供应商设备封装: TO-92-3
包装: 带卷 (TR)
DS1822-PAR
DETAILED PIN DESCRIPTIONS Table 1
PIN
1
2
3
SYMBOL
GND
DQ
NC
DESCRIPTION
Ground.
Data Input/Output pin. Open-drain 1-Wire interface pin. Also provides power
to the device when used in parasite power mode (see “Parasite Power” section.)
No Connect. Doesn’t connect to internal circuit.
OVERVIEW
The DS1822-PAR uses Dallas’ exclusive 1-Wire bus protocol that implements bus communication using
one control signal. The control line requires a weak pullup resistor since all devices are linked to the bus
via a 3-state or open-drain port (the DQ pin in the case of the DS1822-PAR). In this bus system, the
microprocessor (the master device) identifies and addresses devices on the bus using each device’s unique
64-bit code. Because each device has a unique code, the number of devices that can be addressed on one
bus is virtually unlimited. The 1-Wire bus protocol, including detailed explanations of the commands and
“time slots,” is covered in the 1-WIRE BUS SYSTEM section of this data sheet.
An important feature of the DS1822-PAR is its ability to operate without an external power supply.
Power is instead supplied through the 1-Wire pullup resistor via the DQ pin when the bus is high. The
high bus signal also charges an internal capacitor (C PP ), which then supplies power to the device when the
bus is low. This method of deriving power from the 1-Wire bus is referred to as “parasite power.”
Figure 1 shows a block diagram of the DS1822-PAR, and pin descriptions are given in Table 1. The
64-bit ROM stores the device’s unique serial code. The scratchpad memory contains the 2-byte
temperature register that stores the digital output from the temperature sensor. In addition, the scratchpad
provides access to the 1-byte upper and lower alarm trigger registers (T H and T L ). The T H and T L registers
are NV (EEPROM), so they will retain their data when the device is powered down.
DS1822-PAR BLOCK DIAGRAM Figure 1
V PU
4.7K
PARASITE POWER
CIRCUIT
MEMORY CONTROL
LOGIC
DS1822-PAR
DQ
TEMPERATURE SENSOR
GND
INTERNAL V DD
C PP
64-BIT ROM
AND
1-wire PORT
SCRATCHPAD
ALARM HIGH TRIGGER (T H )
REGISTER (EEPROM)
ALARM LOW TRIGGER (T L )
REGISTER (EEPROM)
CONFIGURATION REGISTER
(EEPROM)
8-BIT CRC GENERATOR
2 of 19
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