参数资料
型号: DS1831A+
厂商: Maxim Integrated Products
文件页数: 7/14页
文件大小: 0K
描述: IC MULTIMON 5V/3.3V WDOG 16-DIP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 25
系列: MicroMonitor™
类型: 多压监控器
监视电压数目: 3
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 10 ms;100 ms;1,000 ms
电压 - 阀值: 3.3V,5V,可调
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 16-DIP(0.300",7.62mm)
供应商设备封装: 16-PDIP
包装: 管件
DS1831/A/B
OUTPUT VALID CONDITIONS
The DS1831 can maintain valid outputs as long as one input remains above 1.0V. Accurate voltage
monitoring additionally requires that either the 3.3V IN or 5V IN input be above 1.5V. If this condition is
not met and at least one of the supply inputs are at or above 1.0V all outputs are maintained in the active
condition. The DS1831 requires pull-up resistors on the outputs to maintain a valid output. The value of
the pull up resistor is not critical in most cases but must be set low enough to pull the output to a high
state. A common pull-up resistor value used is 10k W (see Figure 7).
APPLICATION DIAGRAM—OPEN DRAIN OUTPUTS Figure 7
5V Supply
3.3V Supply
10 K W
IN 5V
RST 5V
TOL 5V
TD 5V
PBRST 5V
1
2
3
4
5
16
DS1831 15
14
13
12
IN 3.3v
RST 3.3V
TOL 3.3V
TD 3.3V
PBRST 3.3V
10 k W
GND
NOTE: If outputs are at different voltages the outputs can not be connected to form a wired AND.
OPERATION—NON-MASKABLE INTERRUPT
The DS1831 has two referenced comparator (DS1831A has only one referenced comparator) that can be
used to monitor upstream voltages or other system specific voltages. Each comparator is referenced to the
1.25V internal band gap reference and controls an open-drain output. When a voltage being monitored
decays to the voltage sense point, the DS1831 pulses the NMI output to the active state for a minimum
10μs. The comparator detection circuitry also has built-in hysteresis of 100μV. The supply must be below
the voltage sense point for approximately 2μs before a low NMI will be generated. In this way, power
supply noise is minimized in the monitoring function, reducing false interrupts. See Figure 8 for the non-
maskable timing diagram.
Versatile trip voltages can be configured by the use of an external resistor divider to divide the voltage at
a sense point to the 1.25V trip levels of the referenced comparators. See Figure 9 for an example circuit
diagram and sample equations. The equations demonstrate a design process to determine the resistor
values to use.
Connecting one or both NMI outputs to one of the reset specific PBRST s allows the non-maskable
interrupt to generate an automatic reset for the reset time period when an out-of-tolerance condition
occurs in a monitored supply. An example is shown in Figure 9.
7 of 14
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