参数资料
型号: DS1843D+TRL
厂商: Maxim Integrated Products
文件页数: 3/8页
文件大小: 0K
描述: IC CIRCUIT SAMPLE-N-HOLD 8-UDFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 采样和保持
应用: 光纤学网络
安装类型: 表面贴装
封装/外壳: 8-WFDFN
供应商设备封装: 8-uDFN(2x2)
包装: 带卷 (TR)
DS1843
Fast Sample-and-Hold Circuit
_______________________________________________________________________________________
3
Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are negative.
Note 2: Guaranteed by design.
Note 3: VOUT at the end of the 10s hold time is within specified level of VIN during the sample window; a 50 resistor connected in
series to both VINP and VINN (VINP - VINN = 1V). External capacitance to ground for both VINP and VINN is approximately 10pF.
Note 4: The sampling capacitor must be removed from the input signal before the input signal changes. Therefore, the SEN pin
must be low for a short period of time, tDEL, before the input changes.
Note 5: VOUT at the end of the hold time is within 1% of VIN during the sample window (VINP - VINN = 1V).
Note 6: Voltage step applied across VOUTP to VOUTN through a 5pF capacitor connected to each pin. This models the load presented
by an ADC while it is sampling the DS1843’s output. See the
Output Buffer section. Settled within 1% of initial voltage.
AC ELECTRICAL CHARACTERISTICS
(VCC = +2.97V to +5.5V, TA = -40°C to +85°C, unless otherwise noted.) (See the Timing Diagram.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Sample Time Minimum
tS
VOUT is within 0.4dB (Note 3)
300
ns
Delay Time Minimum
tDEL
(Note 4)
10
ns
Output Time
tOUT
Delay from SEN falling edge until valid
output at VOUT to 1% accuracy
2
s
Hold Time
tHOLD
(Note 5)
tOUT
100
s
1V step, DEN = high
2
Output Step Recovery Time
(Note 6)
tREC
3V step, DEN = high or low
3.5
s
Timing Diagram
VINP - VINN
VOUTP - VOUTN
EXTERNAL
ADC DATA
tADC:ST = EXTERNAL ADC SAMPLING TIME.
tADC:CT = EXTERNAL ADC CONVERSION TIME.
DEN IS CONNECTED TO VCC FOR DIFFERENTIAL OUTPUT.
NOTE: THIS TIMING DIAGRAM IS APPLICABLE FOR SINGLE-ENDED AND DIFFERENTIAL OUTPUT CONFIGURATIONS.
SEN
tS
tDEL
tOUT
tADC:ST
DATA VALID
tADC:CT
tREC
tHOLD
VOLTAGE INVALID
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