- 您现在的位置：买卖IC网 > PDF目录9175 > DS1844E-010+T&R (Maxim Integrated Products)IC POT DIG QUAD 10K 20-TSSOP PDF资料下载
参数资料
| 型号： | DS1844E-010+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 9/14页 |
| 文件大小： | 0K |
| 描述： | IC POT DIG QUAD 10K 20-TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 接片： | 64 |
| 电阻（欧姆）： | 10k |
| 电路数： | 4 |
| 温度系数： | 标准值 750 ppm/°C |
| 存储器类型： | 易失 |
| 接口： | 2 线串行（设备位址）或 5 线串行 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 带卷 (TR) |
DS1844
4 of 14
Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line can be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data. Figure 4 details how
data transfer is accomplished on the two-wire bus. Depending upon the state of the R/W bit, two types of
data transfer are possible.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a 9th
bit.
Within the bus specifications a regular mode (100 kHz clock rate) and a fast mode (400 kHz clock rate)
are defined. The DS1844 works in both modes.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition.
1.
Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master
is the command/control byte. Next follows a number of data bytes. The slave returns an
acknowledge bit after each received byte.
2.
Data transfer from a slave transmitter to a master receiver. The 1st byte (the command/control
byte) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a
number of data bytes transmitted by the slave to the master. The master returns an acknowledge
bit after all received bytes other than the last byte. At the end of the last received byte, a ‘not
acknowledge’ can be returned.
The master device generates all serial clock pulses and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated START condition. Since a repeated START condition is
also the beginning of the next serial transfer, the bus will not be released.
The DS1844 may operate in the following two modes:
1.
Slave receiver mode: Serial data and clock are received through SDA and SCL, respectively. After
each byte is received, an acknowledge bit is transmitted. START and STOP conditions are
recognized as the beginning and end of a serial transfer. Address recognition is performed by
hardware after reception of the slave (device) address and direction bit.
2.
Slave transmitter mode: The 1st byte is received and handled as in the slave receiver mode.
However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial
data is transmitted on SDA by the DS1844 while the serial clock is input on SCL. START and
STOP conditions are recognized as the beginning and end of a serial transfer.
相关PDF资料 |
PDF描述 |
|---|---|
| DS1844E-050+T&R | IC POT DIG QUAD 50K 20-TSSOP |
| DS1844E-100+T&R | IC POT DIG QUAD 100K 20-TSSOP |
| MAX5482ETE+ | IC POT DGTL 10BIT NV 16-TQFN |
| MAX5483ETE+ | IC POT DGTL 10BIT NV 16-TQFN |
| DS1868S-50+T&R | IC POT DIGITAL DUAL 50K 16-SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1844E-050 | 功能描述:数字电位计 IC RoHS:否 制造商:Maxim Integrated 电阻:200 Ohms 温度系数:35 PPM / C 容差:25 % POT 数量:Dual 每 POT 分接头:256 弧刷存储器:Volatile 缓冲刷: 数字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作电源电压:1.7 V to 5.5 V 电源电流:27 uA 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:TQFN-16 封装:Reel |
| DS1844E-050/T&R | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:IC POT DIG QUAD 50K 20-TSSOP |
| DS1844E-050/T&R | 功能描述:数字电位计 IC RoHS:否 制造商:Maxim Integrated 电阻:200 Ohms 温度系数:35 PPM / C 容差:25 % POT 数量:Dual 每 POT 分接头:256 弧刷存储器:Volatile 缓冲刷: 数字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作电源电压:1.7 V to 5.5 V 电源电流:27 uA 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:TQFN-16 封装:Reel |
| DS1844E-050+ | 功能描述:数字电位计 IC Quad RoHS:否 制造商:Maxim Integrated 电阻:200 Ohms 温度系数:35 PPM / C 容差:25 % POT 数量:Dual 每 POT 分接头:256 弧刷存储器:Volatile 缓冲刷: 数字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作电源电压:1.7 V to 5.5 V 电源电流:27 uA 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:TQFN-16 封装:Reel |
| DS1844E-050+T&R | 制造商:Maxim Integrated Products 功能描述:DGTL POTENTIOMETER 64POS 50KOHM QUAD 20TSSOP - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC POT DIG QUAD 50K 20-TSSOP |
发布紧急采购，3分钟左右您将得到回复。