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参数资料
| 型号： | DS1844S-100+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 14/14页 |
| 文件大小： | 0K |
| 描述： | IC POT DIG QUAD 100K 20-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1,000 |
| 接片： | 64 |
| 电阻（欧姆）： | 100k |
| 电路数： | 4 |
| 温度系数： | 标准值 750 ppm/°C |
| 存储器类型： | 易失 |
| 接口： | 2 线串行（设备位址）或 5 线串行 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC W |
| 包装： | 带卷 (TR) |
DS1844
9 of 14
5-WIRE SERIAL INTERFACE
AC ELECTRICAL CHARACTERISTICS
(-40°C to +85°C; VCC=2.7V to 5.5V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Port Select Setup
tSETUP
30
ns
14, 21
R/ W Setup
tSETUP
30
ns
14, 21
Clock Frequency
fCLK
DC
5
MHz
14, 15
Width of CLK Pulse
tCH
50
ns
14, 15
Data Setup Time
tDC
30
ns
14, 15
Data Hold Time
tCDH
0
ns
14, 15
Progapation Delay Time High to Low
Level Clock to Output
tDV
40
ns
14, 15
RST High to Clock Input High
tCC
50
ns
14, 15
RST Low from Clock Input High
tHLT
50
ns
14, 15
RST Inactive
tRLT
125
ns
14, 15
CLK Rise Time, CLK Fall Time
tCR
50
ns
14, 15
NOTES:
1.
All voltages are referenced to ground.
2.
I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VCC is switched off.
3.
ICC specified with SDA pin open.
4.
ISTBY specified with for VCC equal 3.0V and 5.0V and control port logic pins are driven to the
appropriate logic levels. Appropriate logic levels specify that logic inputs are within a 0.5-volt of
ground or VCC for the corresponding inactive state.
5.
After this period, the first clock pulse is generated.
6.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
VIH MIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7.
The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW ) of
the SCL.
8.
A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tRMAX + tSU:DAT = 1000+250=1250 ns before the SCL line
is released.
9.
CB - total capacitance of one bus line in picofarads, timing referenced to (0.9)(VCC) and (0.1)
(VCC).
10.
Typical values are for ta = 25°C and nominal supply voltage.
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