参数资料
型号: DS1855E-C01+T&R
厂商: Maxim Integrated Products
文件页数: 7/21页
文件大小: 0K
描述: IC DUAL NV DGTL POT/MEM 14-TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1,000
接片: 100,256
电阻(欧姆): 10k
电路数: 2
温度系数: 标准值 750 ppm/°C
存储器类型: 非易失
接口: I²C(设备位址)
电源电压: 2.7 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 14-TSSOP
包装: 带卷 (TR)
DS1855
15 of 21
NOTES:
1. All voltages are referenced to ground.
2. ISTBY specified with for VCC = 3.0V and 5.0V, and control port logic pins are driven to the appropriate
logic levels. Appropriate logic levels specify that logic inputs are within a 0.5V of ground or VCC for
the corresponding inactive state.
3. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VCC is switched off.
4. A fast mode device can be used in a standard mode system, but the requirement t
SU:DAT > 250ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line tRMAX + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released.
5. After this period, the first clock pulse is generated.
6. The maximum t
HD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL signal.
7. CB – Total capacitance of one bus line in picofarads, timing referenced to 0.9 x V
CC and 0.1 x VCC.
8. EEPROM write begins after a STOP condition occurs.
9. Absolute linearity is used to measure expected wiper voltage as determined by wiper position.
10. Relative linearity is used to determine the change of wiper voltage between two adjacent wiper
positions.
11. ICC specified with SDA pin open.
12. Maximum ICC is dependent on clock rates.
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