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参数资料
| 型号： | DS1859E-050/T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 5/28页 |
| 文件大小： | 0K |
| 描述： | IC RES TEMP 50/50K 3MON 16-TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1,000 |
| 接片： | 256 |
| 电阻（欧姆）： | 50k |
| 电路数： | 2 |
| 温度系数： | 标准值 50 ppm/°C |
| 存储器类型： | 非易失 |
| 接口： | I²C（设备位址） |
| 电源电压： | 2.85 V ~ 5.5 V |
| 工作温度： | -40°C ~ 95°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
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DS1859
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
____________________________________________________________________
13
MEMORY LOCATION
(hex)
EEPROM/SRAM
R/W
DEFAULT SETTING
(hex)
NAME OF LOCATION
FUNCTION
00 to 7F
EEPROM
R/W
00
Standards Data
—
Auxiliary Device
MEMORY
LOCATION
(hex)
EEPROM/
SRAM
R/W
DEFAULT
SETTING
(hex)
NAME OF LOCATION
FUNCTION
00 to 01
EEPROM
R/W
00
TMPlimhi (MSB to LSB)
Contains upper limit settings for temperature.
If the limit is violated, an alarm flag in Main
Device byte 70h is set.
02 to 03
EEPROM
R/W
00
TMPlimlo (MSB to LSB)
Contains lower limit settings for temperature. If
the limit is violated, an alarm flag in Main
Device byte 70h is set.
04 to 05
EEPROM
R/W
00
TMPwrnhi (MSB to LSB)
Contains upper limit settings for temperature.
If the limit is violated, a warning flag in Main
Device byte 74h is set.
06 to 07
EEPROM
R/W
00
TMPwrnlo (MSB to LSB)
Contains lower limit settings for temperature. If
the limit is violated, a warning flag in Main
Device byte 74h is set.
08 to 09
EEPROM
R/W
00
VCClimhi (MSB to LSB)
Contains upper limit settings for VCC. If the
limit is violated, an alarm flag in Main Device
byte 70h is set.
0A to 0B
EEPROM
R/W
00
VCClimlo (MSB to LSB)
Contains lower limit settings for VCC. If the
limit is violated, an alarm flag in Main Device
byte 70h is set.
0C to 0D
EEPROM
R/W
00
VCCwrnhi (MSB to LSB)
Contains upper limit settings for VCC. If the
limit is violated, a warning flag in Main Device
byte 74h is set.
0E to 0F
EEPROM
R/W
00
VCCwrnlo (MSB to LSB)
Contains lower limit settings for VCC. If the
limit is violated, a warning flag in Main Device
byte 74h is set.
10 to 11
EEPROM
R/W
00
MON1limhi (MSB to LSB)
Contains upper limit settings for MON1. If the
limit is violated, an alarm flag in Main Device
byte 70h is set.
Main Device
Note: SRAM defaults are power-on defaults. EEPROM defaults are factory defaults.
Register Map
A description of the registers is below. The registers
are read only (R) or read/write (R/W). The R/W registers
are writable only if write protect has not been asserted
(see the Memory Description section).
Bytes designated as "Reserved" have been set aside
for added functionality in future revisions of this device.
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