参数资料
型号: DS1868-50
厂商: Maxim Integrated Products
文件页数: 8/14页
文件大小: 0K
描述: IC POT DIGITAL DUAL 50K 14-DIP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 25
接片: 256
电阻(欧姆): 50k
电路数: 2
温度系数: 标准值 750 ppm/°C
存储器类型: 易失
接口: 3 线串口
电源电压: 2.7 V ~ 3.3 V,4.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 14-DIP(0.300",7.62mm)
供应商设备封装: 14-PDIP
包装: 管件
DS1868
3 of 14
DS1868 BLOCK DIAGRAM Figure 1
I/O SHIFT REGISTER Figure 2
Transmission of data always begins with the stack select bit followed by the potentiometer-1 wiper
position value and lastly the potentiometer-0 wiper position value.
When wiper position data is to be written to the DS1868, 17 bits (or some integer multiple) of data should
always be transmitted. Transactions which do not send a complete 17 bits (or multiple) will leave the
register incomplete and possibly an error in the desired wiper positions.
After a communication transaction has been completed the RST signal input should be taken to a low
state to prevent any inadvertent changes to the device shift register. Once RST has reached a low state,
the contents of the I/O shift register are loaded into the respective multiplexers for setting wiper position.
A new wiper position will only engage after a RST transition to the inactive state. On device power-up,
wiper position will be random.
STACKED CONFIGURATION
The potentiometers of the DS1868 can be connected in series as shown in Figure 3. This is referred to as
the stacked configuration and allows the user to double the total end-to-end resistance of the part. The
resolution of the combined potentiometers will remain the same as a single potentiometer but with a total
of 512 wiper positions available. Device resolution is defined as RTOT /256 (per potentiometer); where
RTOT equals the total potentiometer resistance.
The wiper output for the combined stacked potentiometer will be taken at the SOUT pin, which is the
multiplexed output of the wiper of potentiometer-0 (W0) or potentiometer-1 (W1). The potentiometer
wiper selected at the SOUT output is governed by the setting of the stack select bit (bit 0) of the 17-bit I/O
shift register. If the stack select bit has value 0, the multiplexed output, SOUT, will be that of the
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