参数资料
型号: DS1877T+T&R
厂商: Maxim Integrated Products
文件页数: 15/65页
文件大小: 0K
描述: IC CTLR/MON SFP 1-2CH 28TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: SFP+ 控制器
输入类型: 逻辑
输出类型: 逻辑
接口: I²C
电流 - 电源: 2.5mA
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 带卷 (TR)
其它名称: 90-1877T+TRL
22
Maxim Integrated
SFP Controller for Dual Rx Interface
DS1877
To prevent address wrapping from occurring, the
master must send a STOP condition at the end of
the page, then wait for the bus-free or EEPROM write
time to elapse. Then the master can generate a new
START condition and write the slave address byte
(R/W = 0) and the first memory address of the next
memory row before continuing to write data.
Acknowledge Polling: Any time a EEPROM page is
written, the device requires the EEPROM write time
(tWR) after the STOP condition to write the contents of
the page to EEPROM. During the EEPROM write time,
the device does not acknowledge its slave address
because it is busy. It is possible to take advantage
of that phenomenon by repeatedly addressing the
device, which allows the next page to be written as
soon as the device is ready to receive the data. The
alternative to acknowledge polling is to wait for maxi-
mum period of tWR to elapse before attempting to
write again to the device.
EEPROM Write Cycles: When EEPROM writes
occur, the device writes the whole EEPROM memory
page, even if only a single byte on the page was
modified. Writes that do not modify all 8 bytes on the
page are allowed and do not corrupt the remaining
bytes of memory on the same page. Because the
whole page is written, bytes on the page that were
not modified during the transaction are still subject to
a write cycle. This can result in a whole page being
worn out over time by writing a single byte repeatedly.
Writing a page 1 byte at a time wears the EEPROM
out 8x faster than writing the entire page at once. The
device’s EEPROM write cycles are specified in the
Nonvolatile Memory Characteristics table. The speci-
fication shown is at the worst-case temperature. It can
handle approximately 10x that many writes at room
temperature. Writing to SRAM-shadowed EEPROM
memory with SEEB = 1 does not count as a EEPROM
write cycle when evaluating the EEPROM’s estimated
lifetime.
Figure 13. Example I2C Timing
START
STOP
SLAVE
ACK
SLAVE
ACK
STOP
SINGLE-BYTE WRITE
-WRITE 00h TO REGISTER BAh
TWO-BYTE WRITE
-WRITE 01h AND 75h TO
REGISTERS C8h AND C9h
SINGLE-BYTE READ
-READ REGISTER BAh
TWO-BYTE READ
-READ C8h AND C9h
REPEATED
START
MASTER
NACK
1 0 1 0 0 0 1 0
A2h
1 0 1 1 1 0 1 0
BAh
SLAVE
ACK
START
SLAVE
ACK
1 0 1 0 0 0 1 0
A2h
1 0 1 0 0 0 1 1
A3h
1 0 1 1 1 0 1 0
BAh
SLAVE
ACK
SLAVE
ACK
STOP
0 0 0 0 0 0 0 0
00h
STOP
SLAVE
ACK
STOP
0 1 1 1 0 1 0 1
75h
START
SLAVE
ACK
1 0 1 0 0 0 1 0
A2h
1 1 0 0 1 0 0 0
C8h
SLAVE
ACK
SLAVE
ACK
0 0 0 0 0 0 0 1
01h
SLAVE
ACK
DATA IN BAh
DATA
REPEATED
START
MASTER
ACK
START
SLAVE
ACK
1 0 1 0 0 0 1 0
A2h
1 0 1 0 0 0 1 1
A3h
1 1 0 0 1 0 0 0
C8h
SLAVE
ACK
SLAVE
ACK
DATA IN C8h
DATA
MASTER
NACK
DATA IN C9h
DATA
EXAMPLE I2C TRANSACTIONS WITH A2h AS THE MAIN MEMORY DEVICE ADDRESS
*IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY AND A2h/B2h FOR THE MAIN MEMORY.
IF ASEL = 1, THE SLAVE ADDRESS IS DETERMINED BY TABLE 02h, REGISTER 8Bh FOR THE MAIN MEMORY. THE AUXILIARY MEMORY CONTINUES TO BE ADDRESSED AT A0h, EXCEPT WHEN THE PROGRAMMED
ADDRESS FOR THE MAIN MEMORY IS A0h.
TYPICAL I2C WRITE TRANSACTION
A)
C)
B)
D)
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
REGISTER ADDRESS
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
DATA
SLAVE
ACK
SLAVE
ACK
SLAVE
ADDRESS*
X
0
1
R/W
MSB
LSB
READ/
WRITE
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