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参数资料
| 型号： | DS18S20Z/T&R |
| 厂商： | Maxim Integrated |
| 文件页数： | 13/23页 |
| 文件大小： | 0K |
| 描述： | IC THERM MICROLAN HI-PREC 8-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 感应温度： | -55°C ~ 125°C |
| 输出类型： | 数字 |
| 电源电压： | 3 V ~ 5.5 V |
| 精确度： | ±0.5°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
DS18S20
1-WIRE SIGNALING
The DS18S20 uses a strict 1-Wire communication protocol to ensure data integrity. Several signal types
are defined by this protocol: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. All these
signals, with the exception of the presence pulse, are initiated by the bus master.
INITIALIZATION PROCEDURE—RESET AND PRESENCE PULSES
All communication with the DS18S20 begins with an initialization sequence that consists of a reset pulse
from the master followed by a presence pulse from the DS18S20. This is illustrated in Figure 10. When
the DS18S20 sends the presence pulse in response to the reset, it is indicating to the master that it is on
the bus and ready to operate.
During the initialization sequence the bus master transmits (T X ) the reset pulse by pulling the 1-Wire bus
low for a minimum of 480 μ s. The bus master then releases the bus and goes into receive mode (R X ).
When the bus is released, the 5k ? pullup resistor pulls the 1-Wire bus high. When the DS18S20 detects
this rising edge, it waits 15 μ s to 60 μ s and then transmits a presence pulse by pulling the 1-Wire bus low
for 60 μ s to 240 μ s.
Figure 10. Initialization Timing
V PU
MASTER T X RESET PULSE
480 μ s minimum
DS18S20
waits 15-60 μ s
MASTER R X
480 μ s minimum
DS18S20 T X
presence pulse
60-240 μ s
1-WIRE BUS
GND
LINE TYPE LEGEND
Bus master pulling low
DS18S20 pulling low
Resistor pullup
READ/WRITE TIME SLOTS
The bus master writes data to the DS18S20 during write time slots and reads data from the DS18S20
during read-time slots. One bit of data is transmitted over the 1-Wire bus per time slot.
WRITE TIME SLOTS
There are two types of write time slots: “Write 1” time slots and “Write 0” time slots. The bus master
uses a Write 1 time slot to write a logic 1 to the DS18S20 and a Write 0 time slot to write a logic 0 to the
DS18S20. All write time slots must be a minimum of 60 μ s in duration with a minimum of a 1 μ s recovery
time between individual write slots. Both types of write time slots are initiated by the master pulling the
1-Wire bus low (see Figure 11).
To generate a Write 1 time slot, after pulling the 1-Wire bus low, the bus master must release the 1-Wire
bus within 15 μ s. When the bus is released, the 5k ? pullup resistor will pull the bus high. To generate a
Write 0 time slot, after pulling the 1-Wire bus low, the bus master must continue to hold the bus low for
the duration of the time slot (at least 60 μ s). The DS18S20 samples the 1-Wire bus during a window that
lasts from 15 μ s to 60 μ s after the master initiates the write time slot. If the bus is high during the sampling
window, a 1 is written to the DS18S20. If the line is low, a 0 is written to the DS18S20.
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